• ETRI Journal
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• v.29 no.1
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• pp.45-49
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• 2007

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.621-622
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• 2006

This paper presents the design of LVDS(Low-Voltage-Differential-Signaling) driver circuit for Gb/s-per-pin operation using BiCMOS process technology. To reduce chip area, LVDS driver's switching devices were replaced with lateral bipolar devices. The designed lateral bipolar transister's common emitter current gain($\beta$) is 20 and device's emitter size is 2*10um. Also the proposed LVDS driver is operated at 2.5V and the maximum data rate is 2.8Gb/s approximately.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.879-886
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• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1069-1072
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• 2002

고도로 발달된 정보화 시대에서 우리가 원하는 정보를 짧은 시간, 적은 비용으로 서로 주고 받기 위해서는 이것에 맞는 시스템이 요구된다. 반도체 chip의 대용량과 고속화됨으로써 TTL, ,LVTTL등이 data 100Mbps 정도를 안전하게 전달 할 수 있는 능력이 있으므로 그 이상을 전달할 수 있는 새로운 Logic level이 필요하게 되었다. 이에 맞추어 신호 level의 여러 가지 중 본 논문에서는 Virtex II XC2V 1000 FF896을 이용하여 Differential I/O LVDS( Low Voltage Differential Signaling ) level 특성을 clock, Data와의 전송관계를 Eye_Pattern을 통해 살펴보았다.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• Proceedings of the KAIS Fall Conference
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• 2002.05a
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• pp.215-217
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• 2002

본 논문에서는 CM-MVL(Current Mode Multi-Valued Logic)을 이용한 Host와 LCD Controller 간에 인터페이스 회로를 제안한다. 제안한 회로는 기존의 LVDS(Low Voltage Differential Signaling)과 TMDS(Transition Minimized Differential Signaling)와 같은 전류 특성을 가지며, 3비트 동시 전송이 가능하여 동일한 전송 속도 하에서 보다 많은 데이터를 전송할 수 있다. 그리고 전류에 의한 데이터 전송을 통하여 노이즈에 강한 특성을 나타낸다. 제안한 회로는 HSPICE 시뮬레이션을 통해서 회로의 동작을 확인하였다.

• Journal of Digital Convergence
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• v.10 no.11
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• pp.371-376
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• 2012

In this paper, we propose a new data coding method and its circuits for minimizing data transition in text image. The proposed circuits can solve the synchronization problem between input data and output data in the modified LVDS algorithm. And the proposed algorithm is allowed to transmit two data signals through additional serial data coding method in order to minimize the data transition in text image and can reduce the operating frequency to a half. Thus, we can solve EMI(Electro-Magnetic Interface) problem and reduce the power consumption. The simulation results show that the proposed algorithm and circuits can provide an enhanced data transition minimization in text image and solve the synchronization problem between input data and output data.