• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1437-1439
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• 1999

This paper describes test method though low voltage power system implementation for high impedance fault relay test before its operation in real power system. Through this test, relay tested its function and algorithm. In this paper, we will provides test method using low voltage power system and its results.

• 한국HCI학회:학술대회논문집
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• 2008.02a
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• pp.280-285
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• 2008

ZigBee is Low Power and Low Data Rate Wireless Communication protocol. It apply to much Ubiquitous Sensor Network. ZigBee PAN is two type PAN. One is Beacon Enabled PAN, the other is Non Beacon Enabled PAN. To support Low Power in Non Beacon Enabled PAN, End-Device enter Active status at End-Device's wishing time and send a data. So, Router does not know End-Device sends a data time. To solving this problem, Router must always exist to Active status. In this case, Router receive a power supply always in Non Beacon Enabled PAN. But Router does not receive a power supply always, Router can not normal operation, such as Router use a battery. To solve this problem, Router will be support low power. In this paper, we will present Router's Low Power Algorithm. And we suggest 'PAN Time'. Device use 'PAN Time' for PAN synchronous. Router using Low Power Algorithm can be enter to inactive status. So Non Beacon Enabled PAN of Router support the low power mode Therefore Router does not receive a power supply always, Router can normal operation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• ETRI Journal
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• v.25 no.5
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.251-258
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• 1994

To apply the Power MOSFET to the high powerd circuits, the parallel operation of the Power MOSFET must be considered because of their low power rating. This means, in practical applications, design methods for the parallel operations are required. However, it is very difficult to investigate the problem of parallel operations by directly changing the internal parameters of the MOSFET. Thus, in this paper, the effects of internal parameters for the parallel operation are investigated using SPICE program which is often used and known that the program is very reliable. The investigation results show that while the gate resistance and gate capacitances are the parameters which affect to the dynamic switching operations, the drain and source resistances are the parameters which affect to the steady-state current unbalances. Through this investigation, the design methods for the parallel operation of the MOSFET are suggested, which, in turn, contributes to the practical use of Power MOSFETs.

• Journal of the Korea Society of Computer and Information
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• v.24 no.3
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• pp.29-39
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• 2019

In this study, we introduce a model that satisfies energy efficiency and economical efficiency by introducing and demonstrating cogeneration generators in industrial complexes using various actual data collected at the site. The proposed model is composed of three scenarios, ie, full - time operation, scenario operated according to demand, and a fusion type. In this study, the power generation profit and surplus thermal energy are measured according to the operation of the generator, and the thermal energy is traded according to the demand of the customer to calculate the profit and loss including the heat and evaluate the economic efficiency. As a result of the study, it is relatively profitable to reduce the generation of the generator under the condition that the electricity rate is low and the gas rate is high, while the basic charge is not increased. On the contrary, if the electricity rate is high and the gas rate is low, The more you start up, the more profit you can see. These results show that even a cogeneration power plant with a low economic efficiency due to a low "spark spread" has sufficient economic value if it can sell more than a certain amount of heat energy from a nearby customer and adjust the applied power through peak management.

• Journal of Electrical Engineering and Technology
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• v.1 no.2
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• pp.216-225
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• 2006

This paper presents a new circuit topology of DC busline switch and snubbing capacitor-assisted full-bridge soft-switching PWM inverter type DC-DC power converter with a high frequency link for low voltage large current applications as DC feeding systems, telecommunication power plants, automotive DC bus converters, plasma generator, electro plating plants, fuel cell interfaced power conditioner and arc welding power supplies. The proposed power converter circuit is based upon a voltage source-fed H type full-bridge high frequency PWM inverter with a high frequency transformer link. The conventional type high frequency inverter circuit is modified by adding a single power semiconductor switching device in series with DC rail and snubbing lossless capacitor in parallel with the inverter bridge legs. All the active power switches in the full-bridge inverter arms and DC busline can achieve ZVS/ZVT turn-off and ZCS turn-on commutation operation. Therefore, the total switching losses at turn-off and turn-on switching transitions of these power semiconductor devices can be reduced even in the high switching frequency bands ranging from 20 kHz to 100 kHz. The switching frequency of this DC-DC power converter using IGBT power modules is selected to be 60 kHz. It is proved experimentally by the power loss analysis that the more the switching frequency increases, the more the proposed DC-DC converter can achieve high performance, lighter in weight, lower power losses and miniaturization in size as compared to the conventional hard switching one. The principle of operation, operation modes, practical and inherent effectiveness of this novel DC-DC power converter topology is proved for a low voltage and large current DC-DC power supplies of arc welder applications in industry.

• Journal of the Korean Solar Energy Society
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• v.32 no.3
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• pp.19-25
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• 2012

About supply and demand to see that you need to match, the limitations of wind power capacity is low demand and the commitment of the general generator will exist between the minimum generation. if the turbine's output can be controlled, The limitation of wind power capacity will be adopted based on instant power generation. Namely, The minimum limits of wind power generation based load operation by calculating the amount that is higher than if the output should be restricted to highest operation. in this paper, we committed to the demand for low enough that the combination of the general generator of wind power capacity to accommodate the operation of determining whether the limit is intended to. For this, power system analysis program PSS/E was used, Jeju system by implementing the model simulations were performed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).