• Industrial Engineering and Management Systems
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• v.7 no.1
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• pp.78-89
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• 2008

The need for holistic modeling efforts for returns that capture the extended closed loop supply chain (CLSC) system at strategic as well as operational level has been clearly recognized by the industry and academia. Strategic decision-makers need comprehensive models that can guide them in efficient decision-making to increase the profitability of the entire forward and return chain. Therefore, determination of a near optimal design configuration, which includes the environmental, economical and technological capability factors, is important in strategic decision-making effort that affect the profitability of the closed loop supply chain. In this paper, we adopted an improved system dynamics methodology to tackle strategic issues that affect various performance measures, like market, time/cost, environment etc., for closed loop supply chains. After studying real life implementation issues in CLSC design, we presented guidelines for the PBM (Participative Business Modeling) methodology and presented its extension for the strategic dynamic system modeling of return chains. Finally, we demonstrated the measurement of operational performance by extending SD (system dynamic) application to closed loop supply chain management.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.5
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• pp.227-237
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• 2019

Ultra-low latency control is one of the characteristics of 5G cellular network services, which means that the control loop is handled in milliseconds. To achieve this, it is necessary to identify time delay factors that occur in all components related to CPS control loop, including new 5G cellular network elements such as MEC, and to optimize CPS control loop in real time. In this paper, a novel CPS architecture for ultra-low latency control of CPS is designed. We first define the ultra-low latency characteristics of CPS and the CPS concept model, and then propose the design of the control loop performance monitor (CLPM) to manage the timing information of CPS control loop. Finally, a case study of MEC-based implementation of ultra-low latency CPS reviews the feasibility of future applications.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.16-24
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• 2021

Solar array simulator (SAS) is essential equipment in testing and evaluating the power processing performance of a power conditioning system. However, the nonlinearity in the current(I)-voltage(V) characteristic makes the control loop design of SAS a challenging task. Conventionally, only the inner loop is usually considered in the control design approach. However, this study proves that the reference generation loop also interacts with the inner loop and plays a key role in the overall performance of the SAS. In this paper, the performance of voltage-mode control and impedance control, which are two of the most popular architectures for the SAS system, are reviewed and compared by multi-loop analysis.

• Nuclear Engineering and Technology
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• v.55 no.1
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• pp.353-363
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• 2023

The STELLA-2 is a large-scale sodium thermal-hydraulic integral effect test facility and supports the development of PGSFR. The facility adopted Pump Simulation Loop System (PSLS) concept for the mechanical sodium pump in the reference reactor to control and to measure the primary sodium flow. Since the component (mechanical pump) is replaced by the loop, it is very important to evaluate the similarity between the pump and the loop. In this paper, to simulate the characteristic of the mechanical sodium pump, the pressure loss along the various options of the loop was evaluated and the comprehensive validity of each design options was analyzed. Using the similarity criteria based on the Richardson number and Euler number conservation, the PSLS design was finalized and the result was within the acceptable error range. Finally, the result of this study was used for construction of the overall facility, STELLA-2.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.76-85
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• 1997

Charge-pump loop filter was designed using GaAs MESFET for GHz-range PLL system applications. Characteristics of charge-pump loop filter and stability of charge-pump PLL, system were analyzed. Performance specifications were defined and a charge-pump loop filter was designed that satisfies these specifications.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.431-436
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• 1987

In this paper, the development of an One Loop Controller is described. The functions which are built in the One Loop Controller are summarized and the hardware implemention of these functions using 16 bit microprocessor is described. The developed One Loop Controller is applied to DC_Motor based position control system and it's results are given.

• Journal of the Korean Society for Precision Engineering
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• v.11 no.5
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• pp.66-74
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• 1994

A loop-shaping LQ controller is synthesized for tandem cold mills. And a new loop- shaping technique is suggested for LQ controller design. The suggested loop-shaping LQ control system is compared with the standard loop-shaping LQ control system. The simulation results show that the theickness and interstand tension control accuracy of tandem cold mills can be improved by the compensated loop-shaping LQ controller.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.517-526
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• 1987

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

• Journal of ILASS-Korea
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• v.8 no.1
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• pp.23-28
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• 2003

When a cold HPSI (High Pressure Safety Injection) fluid associated with a design basis accident, such as LOCA (Loss of Coolant Accident), enters the cold legs of a stagnated primary coolant loop, thermal stratification phenomena may arise due to incomplete mixing. If the stratified flow enters a reactor pressure vessel downcomer, severe thermal stresses are created in a radiation embrittled vessel wall by local overcooling. Previous thermal-mixing analyses have assumed that the thermal stratification phenomena generated in stagnated loop of a partially stagnated collant loop are neutralized in the vessel downcomer by strong flow from unstagnated loop. On the basis of these reasons, this paper presents the thermal-mixing analysis results in order to identify the fact that the cold plume generated in the vessel downcomer due to the thermal stratification phenomena of the stagnated loop is affected by the strong flow of the unstagnated loop.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.96-101
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• 2003

This paper is on the user equipment (UE) side time tracker design and implementation of the wideband code division multiple access (WCDMA) system. The time tracker is constructed as a second order closed loop including time error detector (TED), loop filter (LP), numerically controlled oscillator (NCO), and sample selector (SS). Through the simulation, we found the gain of the TED as a function of the CPICH power contribution to the total transmission power of the base station. Also we derived the transfer function of the loop and the BER versus DPCH power relationships where timing offsets and loop noise bandwidths are used as parameters. In the curve, we can conclude that there are appropriate loop noise bandwidths according to the given environments for the better performance.