Testable Design for Zipper CMOS Circuits

고장 검풀이 용이한 Zipper CMOS 회로의 설계

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.