• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.70-81
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• 2002

This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.

• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.10
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• pp.1494-1498
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• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.382-383
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• 2013

Gate-controlled spin-orbit interaction parameter is a key factor for developing spin-Field Effect Transistor (Spin-FET) in a quantum well structure because the strength of the spin-orbit interaction parameter decides the spin precession angle [1]. Many researches show the control of spin-orbit interaction parameter in n-type quantum channels, however, for the complementary logic device p-type quantum channel should be also necessary. We have calculated the spin-orbit interaction parameter and the effective mass using the Shubnikov-de Haas (SdH) oscillation measurement in a GaSb two-dimensional hole gas (2DHG) structure as shown in Fig 1. The inset illustrates the device geometry. The spin-orbit interaction parameter of $1.71{\times}10^{11}$ eVm and effective mass of 0.98 $m^0$ are obtained at T=1.8 K, respectively. Fig. 2 shows the gate dependence of the spin-orbit interaction parameter and the hole concentration at 1.8 K, which indicates the spin-orbit interaction parameter increases with the carrier concentration in p-type channel. On the order hand, opposite gate dependence was found in n-type channel [1,2]. Therefore, the combined device of p- and n-type channel spin transistor would be a good candidate for the complimentary logic device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).