References
- G. E. Moore, 'Cramming more components onto integrated circuits', Electronics, Vol. 38, No. 8, pp. 114-117, April 19, 1965
- M. T. Bohr, 'Nanotechnology Goals and Challenges for Electronic Applications', IEEE Trans. Nanotechnology, Vol. 1, No. 1., pp. 56-62, 2002 https://doi.org/10.1109/TNANO.2002.1005426
- S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and P. Avouris, 'Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes', Appl. Phys. Lett., Vol. 80, pp. 3817-3819, 2002 https://doi.org/10.1063/1.1480877
- M. Radosavljevic, S. Heinze, J. Tersoff, and P. Avouris, 'Drain voltage scaling in carbon nanotube transistors', Appl. Phys. Lett., Vol. 83, pp. 2435-2437, 2003 https://doi.org/10.1063/1.1610791
- L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber, 'Epitaxial core-shell and core-multishell nanowire heterostructures', Nature, Vol. 420, pp. 57-61, 2002 https://doi.org/10.1038/nature01141
-
Y. Yamashita, A. Endoh, K. Shinohara, K. Hikosaka, T. Matsui, and S. Hiyamizu, 'Pseudomorphic
$In_{0.52}Al_{0.48}As/In_{0.7}Ga_{0.3}As$ HEMTs With an Ultrahigh$f_T$ of 562 GHz', IEEE Electron Device Letters, Vol. 23, No. 10, pp. 573-575, 2002 https://doi.org/10.1109/LED.2002.802667 - K. Murata, K. Sano, H. Kitabayashi, S. Sugitani, H. Sugahara, and T. Enoki, '100-Gb/s Multiplexing and Demultiplexing IC Operations in InP HEMT Technology', IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, pp. 207-213, 2004 https://doi.org/10.1109/JSSC.2003.820854
-
D. Streit, R. Lai, A. Oki, and A. Gutierrez-Aitken, 'InP HEMT and HBT Applications Beyond 200 GHz', in Proc.
$14^{th}$ IEEE Indium Phosphide and Related Material Conference (IPRM), pp. 11-14, May 2002 https://doi.org/10.1109/ICIPRM.2002.1014077 - C. W. Pobanz, M. Matloubian, M. Lui, H.-C. Sun, M. Case, C. M. Ngo, P. Janke, T. Gaier, and L. Samoska, 'A High-Gain Monolithic D-Band InP HEMT Amplifier', IEEE Journal of Solid-State Circuits, Vol. 34, No. 9, pp. 1219-1224, 1999 https://doi.org/10.1109/4.782079
-
K. Shinohara, Y. Yamashita, A. Endoh, I. Watanabe, K. Hikosaka, T. Mimura, S. Hiyamizu, T. Matsui, 'Nanogate InP-HEMT Technology for Ultrahigh-Speed Performance', in
$16^{th}$ IEEE Indium Phosphide and Related Materials Conference (IPRM), pp. 721-726, May 2004 https://doi.org/10.1109/ICIPRM.2004.1442827 - T. Suemitsu, H. Yokoyama, T. Ishii, T. Enoki, G. Meneghesso, and E. Zanoni, '30-nm Two-Step Recess Gate InP-Based InAlAs/InGaAs HEMTs', IEEE Tran. Electron Devices, Vol. 49, No. 10, pp. 1694-1700, 2002 https://doi.org/10.1109/TED.2002.803646
-
D.-H. Kim, J. A. del Alamo, J.-H. Lee, and K.-S. Seo, 'The Impact of Side-Recess Spacing on the Logic Performance of 50 nm
$In_{0.7}Ga_{0.3}As$ HEMTs', in$18^{th}$ IEEE Indium Phosphide and Related Materials Conference (IPRM), pp. 177-180, May 2006 -
T. Suemitsu, H. Yokoyama, Y. Umeda, T. Enoki, and Y. Ishii, 'High-Performance
$0.1-{\mu}m$ Gate Enhancement-Mode InAlAs/InGaAs HEMT's Using Two-Step Recessed Gate Technology', IEEE Tran. Electron Devices, Vol. 46, No. 6, pp. 1074-1080, 1999 https://doi.org/10.1109/16.766866 - R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, 'Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications', IEEE Trans. Nanotechnology, Vol. 4, No. 2, pp. 153-158, 2005 https://doi.org/10.1109/TNANO.2004.842073
-
S. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, P. Nguyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, M. Bohr, 'A 90 nm Logic Technology Featuring 50 nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1
${\mu}m^2$ SRAM Cell', in Int. Electron Devices Meeting Tech. Dig., pp. 61-64, December 2002 https://doi.org/10.1109/IEDM.2002.1175779 - D. R. Greenberg and Jesus A. del Alamo, 'Nonlinear Source and Drain Resistance in Recessed-Gate Heterostructure Field-Effect Transistors', IEEE Tran. Electron Devices, Vol. 43, No. 8, pp. 1304-1306, 1996 https://doi.org/10.1109/16.506784
-
D.-H. Kim, J. A. del Alamo, J.-H. Lee, and K.-S. Seo, 'Performance Evaluation of 50 nm
$In_{0.7}Ga_{0.3}As$ HEMTs For Beyond-CMOS Logic Applications', in Int. Electron Devices Meeting Tech. Dig., pp. 455-458, December 2005