• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.499-500
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• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• 전자공학회논문지A
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• 제29A권8호
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• pp.1-9
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• 1992

Radio data system is a next-generation broadcasting system of digital information communication which multiplexes the digital data into the FM stereo signal in VHF/FM band and provides important and convenient service features. And radio data are composed of groups which are divided into 4 blocks with information word and check word. In this paper, radio data receiver is developed which recovers and process radio data to provide services. Then we confirm that 7dB SNR is required to be 10S0-5TBER of demodulation. Deconding process of shortened-cyclic-decoder has been simulated by computer. Also, the time-compression (by 16 times) method has been adopted for the RDS features post-processing. Via the error probability calculation, simulation and experimentation, the developed receiver system is proved to satisfy the system specification of EBU and implemented by general logic gates and analog circuits.

• 전자공학회논문지A
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• 제32A권1호
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• pp.206-221
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• 1995

Metal-Metal Matrix(M$^{3}$) layout is a recently proposed layout style which uses minimum amount of poly wires for high speed operation. In this paper we propose a method of generating functional modules in M$^{3}$ layout style. In the proposed method the transistors and the input/output lines of the given circuit are first placed in M$^{3}$ layout style and then they are interconnected using two metal layers. We develop a new placement method by simulated annealing, and we modify the well known channel routing method for the interconnections. When we applied our method to several logic circuits, the area of the generated layout is smaller than the ones by the previously known method. Our results also compares favorably to the other layout styles like gate matrix layout.

• 대한전자공학회논문지
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• 제21권4호
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• pp.13-16
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• 1984

본 논문에서는 NAND 또는 NOR 게이트와 같은 기본 셀로 구성되는 1차원 MOS LSI의 칩 면적을 최소화하기 위한 레이아웃 알고리즘을 제안하고 있다. 배열하고자 하는 MOS 게이트들의 최좌측단과 최우측단에 입·출력 신호선을 표시하는 가상 게이트를 각각 설정하여 각 게이트 통과선 수를 최소화함으로써 수평 트랙 수를 최소로 하는 휴리스틱 알고리즘을 제안하고 실제의 논리회로를 택하여 프로그램 실험을 행함으로써 본 논문에서 제안한 알고리즘이 유용함을 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 전자공학회논문지A
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• 제28A권1호
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• pp.52-59
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• 1991

An effective and accurate delay time model is the key problem in the simulation and timing verification of CMOS logic circuits. We propose a semi-analytic CMOW delay time model taking into account the configuration ratio, the input waveform slope and the load capacitance. This model is based on the Schichman Hodges's DC equations and derived on the optimally weighted switching peak current. The parameters necessary for the model calculation are automatically determined from the program. The proposed model is computationally effective and the error is typically within 10% of the SPICEA results. Compared to the table RC model, the accuracy is inproved over two times in average.

• 전자공학회논문지A
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• 제32A권12호
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.235-240
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• 2007

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

• Journal of Advanced Marine Engineering and Technology
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• 제28권2호
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• pp.200-209
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• 2004

The fuzzy control based on $\alpha$-level fuzzy set decomposition. It is known to produce quick response and calculating time of fuzzy inference. This paper derived the embodiment computational algorithm for defuzzification by min-max fuzzy inference and the center of gravity method based on $\alpha$-level fuzzy set decomposition. It is easy to realize the fuzzy controller hardware. based on the calculation formula. In addition. this study proposed a circuit that generates PWM actual signals ranging from fuzzy inference to defuzzification. The fuzzy controller was implemented with mixed analog-digital logic circuit using the computational fuzzy inference algorithm by min-min-max and defuzzification by the center of gravity method. This study confirmed that the fuzzy controller worked satisfactorily when it was applied to the position control of a dc servo system.