JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A SSN-Reduced 5Gb/s Parallel Transmitter

  • Lee, Seon-Kyoo (Department of Electrical Engineering, Pohang University of Science and Technology) ;
  • Kim, Young-Sang (Department of Electrical Engineering, Pohang University of Science and Technology) ;
  • Park, Hong-June (Department of Electrical Engineering, Pohang University of Science and Technology) ;
  • Sim, Jae-Yoon (Department of Electrical Engineering, Pohang University of Science and Technology)
  • Published : 2007.12.31
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Abstract

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

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References

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