• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.10a
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• pp.14-17
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• 1988

Degradation effects observed in nonvolatile MNOS memory devices with in increasing W/E (Write/Erase) cycling were investigated using n-type MNOS capacitors. The results showed that the density of Si-SiO$_2$ interface states and the conductivity of nitride were increased with W/E cycles, therefore the memory retention characteristics of the MNOS memory devices were degraded. Also, annealing of the degraded devices restored the original Si-SiO$_2$ interface states density, but failed to restore the original nitride conductivity. Based on these experimental results, we found that the degradation of memory retention characteristic was affected by the nitride conductivity rather than by Si-SiO$_2$ interface states.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.94.1-94
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• 2002

This paper is concerned with parallel FFT and Quick-Merge Sort. They are implemented on computers interconnected by VMIC 5579 reflective memory and a cluster of workstations (PCs) interconnected via Fast Ethernet. Message passing interface (MPI) parallel library is used for communication in a cluster of workstations. An improved parallel FFT is also presented to decrease an execution time in the case of a small number of hosts. Distributed shared memory (DSM), VMIC 5579 reflective memory (RM), a cluster of workstations (COW) and message passing interface (MPI) parallel library are described.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• The KIPS Transactions:PartD
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• v.11D no.1
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• pp.11-22
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• 2004

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. Consequently, reducing cache misses emerges as the most important issue in current main memory databases, in which CPU speeds have been increasing at 60% per year, compared to the memory speeds at 10% per you. In this paper, we design and implement a main-memory database system for real-time mobile GIS. Our system is composed of 5 modules： the interface manager provides the interface for PDA users； the memory data manager controls spatial and non-spatial data in main-memory using virtual memory techniques； the query manager processes spatial and non-spatial query : the index manager manages the MR-tree index for spatial data and the T-tree index for non-spatial index : the GIS server interface provides the interface with disk-based GIS. The MR-tree proposed propagates node splits upward only if one of the internal nodes on the insertion path has empty space. Thus, the internal nodes of the MR-tree are almost 100% full. Our experimental study shows that the two-dimensional MR-tree performs search up to 2.4 times faster than the ordinary R-tree. To use virtual memory techniques, the memory data manager uses page tables for spatial data, non- spatial data, T-tree and MR-tree. And, it uses indirect addressing techniques for fast reloading from disk.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Korean Journal of Materials Research
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• v.9 no.4
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• pp.419-427
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• 1999

TiNi shape memory alloy was shape memory heat-treated and investigated its mechanical properties with the variation of prestrain. Also 6061 Al matrix composites with TiNi shape memory alloy fiber as reinforcement have been fabricated by Permanent Mold Casting to investigate the microstructures and interface properties. Yield stress of TiNi wire was the most high in the case of before heat-treatment and then decreased as increasing heat-treatment time. In each heat-treatment condition, the yield stress of TiNi wire was not changed with increasing the amount of prestrain. The interface bonding of TiNi/6061Al composite was fine. There was a 2$\mu\textrm{m}$ thickness of diffusion reaction layer at the interface. We could find out that this diffusion reaction layer was made by the mutual diffusion. The diffusion rate from Al base to TiNi wire was faster than that of reverse diffusion and the amount of the diffusion was also a little more than that of reverse.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.5
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• pp.632-638
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• 2005

This paper describes a new data-handing, based on a Spatial Human Interface as human indicator, to the Spatial-Knowledge-Tags (SKT) in the spatial memory the Spatial Human Interface (SHI) is a new system that enables us to facilitate human activity in a working environment. The SHI stores human activity data as knowledge and activity history of human into the Spatial Memory in a working environment as three-dimensional space where one acts, and loads them with the Spatial-Knowledge-Tags(SKT) by supporting the enhancement of human activity. To realize this, the purpose of SHI is to construct new relationship among human and distributed networks computers and sensors that is based on intuitive and simultaneous interactions. In this paper, the specified functions of SKT and the realization method of SKT are explained. The utility of SKT is demonstrated in designing a robot motion control.