• Journal of Biomedical Engineering Research
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• v.12 no.4
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• pp.277-284
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• 1991

This study describes the ambulatory ECG monitoring system for the remote autom atic diagnosis. System: tlardware is based on one chip microcomputer(80c31) and its peripherals which consists of A/D, EPROM, RAM, LCD display and two preamplifiers, Power circuits, control logic circuits. A/D converted data were differentiated and low pass filtered. The detection of QRS complex and R point were accomplished by software algorithm based on adaptive threshold computed on low pass fi:leered signal. Rhythm analysis is performed by RR interval and average RR interval. The performance of QRS detection algorithm is evaluated by using MIT/BIH data base. Using this system, the trends of the arrythmia during the long term could be saved and displayed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.132-139
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• 1993

This paper presents a new performance-driven multi-levelizer which transforms a two-level description into a boolean network of the multilevel structure satisfied with user's costraints, such as chip area, the number of wires and literals, maximum delay, function level, fanin, fanout, etc.. The performance of circuits is estimated by reference to the informations in cell library through the cell mapping phase, and multi-levelization of circuits is constructed by the decomposition using the kernel and factoring concepts. Here, the saving cost of a common subexpression is defined to the sum of area and delay saved, when it is substituted. The experiments with MCNC benchmarks show the efficiency of the proposed method.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3112-3114
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• 2000

Recently. internet applications for efficient cyber education have drawn much interests. The world-wide web provides new opportunities for cyber education over the internet. In this paper, we developed the internet-based educational simulator for design and virtual experiment of the digital logic circuits. The proposed simulator provides the improved learning methods which can enhance the educational efficiency in digital theory. If the students execute the Digital simulator on the web. they can simulate in digital circuits through simple mouse manipulation. The proposed digital simulator can be used so that the students can easily understand the well-known digital principles.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.76-78
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• 2003

We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25％. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15％. The circuit was measured at the liquid helium temperature.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.123-126
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• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.8
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• pp.361-366
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• 2017

For two given logical expressions and, when expression contains the same part of the logical expression as expression, substituting for that part of expression is called a substituted logic expression. If a substituted relation is established between the logical expressions, there is an advantage in that the number of literals used in the whole logical expression can be greatly reduced. However, if the substituted relation is not established, there is no simplification effect obtained from the substituted expression. Previous methods proposed a way to find substituted relations between logical expressions for the given logical expressions themselves, and to calculate substituted expressions if only substitution is possible. In this paper, a new method for performing substitution with addition and revision of logic terms is proposed in order to perform substitution, even though there is no substituted relation between two logic expressions. The proposed method is efficiently implemented using a matrix that finds terms to be added. Then, by covering the matrix that has added terms, substituted logic expressions are found. Experiment results show that the proposed method for several benchmark circuits can reduce the number of literals, compared to existing synthesis tools.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.108-116
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• 1989

The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.