• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.5
• /
• pp.1221-1229
• /
• 1996

This paper proposes a heuristic algorithm for low power implementation of combinational circuits. Selecting an input variable for a given function, the proposed algorithm performs Shannon exansion with respect to the variable to reduce the number of gates in the subcircuit realizing the coffactor function, reducting the power dissipation of the implemented circuit. experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating the circuits consuming the power 48.9% less on the average, when compared to the previous algorithm based on precomputation logic.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.53 no.1
• /
• pp.22-27
• /
• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.5 no.2
• /
• pp.102-107
• /
• 2005

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1972-1975
• /
• 2002

A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.38-49
• /
• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.11
• /
• pp.140-148
• /
• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.1005-1008
• /
• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.29B no.10
• /
• pp.19-26
• /
• 1992

Generally, When we calculate notch angle to eliminate some selected harmonics using PWM inverter, we put the previously analysed notch angle formed by look-up table into memory, or perform the program to claculate notch angle iteratively with Fourier series. But, these methods are very difficult to control the system in real-time. Now, in this paper, we propose a new method to calculate notch angle using Walsh series, design real-time logic circuits which can be applied in 3 phase circuits and make one chip to reduce complexity and size of circuits using VLSI design technique.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.1
• /
• pp.1-11
• /
• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.2
• /
• pp.88-99
• /
• 1992

This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.