• 제어로봇시스템학회:학술대회논문집
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• 1998.10a
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• pp.507-512
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• 1998

It is an interesting area in the field of artificial intelligence to and an analytic model of cooperative structure for multi-agent system accomplishing a given task. Usually it is difficult to design controllers for multi-agent systems without a comprehensive knowledge about the system. One of the way to overcome this limitation is to implement an evolutionary approach to design the controllers. This paper introduces the use of a genetic algorithm to discover a fuzzy logic controller with rules that govern emergent co-operative behavior: A modified genetic algorithm was applied to automating the discovery of a fuzzy logic controller jot multi-agents playing a pursuit game. Simulation results indicate that, given the complexity of the problem, an evolutionary approach to and the fuzzy logic controller seems to be promising.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1476-1480
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• 1987

This paper proposes a design method for SCLA(sequential CMOS Domino Logic Array) using 1-level CMOS Domino Logic and Stable Shift Register Latch. Also an algorithm to generate a test sequence and a test procedure for the SCLA are presented. The SCLA has advantages of low power consumption, high density and high speed, and performs hazard-and race-free logic operation, because of using SSRL(Stable Shift Register Latch). By using the proposed test method, all of stuck-at, cross-point, stuck-on and stuck-open faults in SCLA are detected by short test sequence.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.177-185
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• 1996

This paper describes several algorithms for technolgoy mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improved the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as merging fanin, unified reduction and multiple disjoint decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.1-10
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• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.155-156
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• 2008

In this paper, an interval type-2 fuzzy logic system is designed and compared with a type-1 fuzzy logic system. To compare performance of a type-1 fuzzy logic system with the type-2 fuzzy logic system, we apply type-1 fuzzy logic system and type-2 system to modeling the noised data. Membership function of interval type-2 fuzzy logic system is designed consequents of rules including uncertainty. For general type-2 fuzzy logic system computational complexity is severe. On the other hand, theoretic and arithmetic computations for interval type-2 fuzzy logic systems are very simple.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2258-2263
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• 2003

This paper presents the design and development of an optimal fuzzy logic controller (FLC) for a laser tracking system. An optimal intelligent fuzzy logic controller was founded on integral criterion of the fuzzy models and three-dimensional fuzzy control. Research had been also concentrated on the methods for multivariable fuzzy models for the purposes of real-time process. Simulation results have shown remarkable tracking performance of this fuzzy PID controller.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.677-680
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• 2000

The technique of reinforcement learning algorithm is extended to solve the multiobjective control problem for uncertain dynamic systems. A multiobjective adaptive critic structure is proposed in order to realize a max-min method in the reinforcement learning process. Also, the proposed reinforcement learning technique is applied to a multiobjective satisfactory fuzzy logic controller design in which fuzzy logic subcontrollers are assumed to be derived from human experts. Some simulation results are given in order to show effectiveness of the proposed method.