Logic synthesis for TLU-type FPGA

TLU형 FPGA를 위한 논리 설계 알고리즘

This paper describes several algorithms for technolgoy mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improved the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as merging fanin, unified reduction and multiple disjoint decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.