• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.599-603
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• 1988

In this paper, a flash type A/D converter using Variable Threshold Logic circuit is designed and is layonted by double metal CMOS 2 um design rule. Comparator and register string which is the basic elements of a general flash type A/D converter are substituted by simple comparator circuit which is slightly modified from cmos inverter.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.278-281
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• 1988

This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.501-503
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• 2005

The improvement of load following operation of the thermal power plant is influenced to the electrical quality. Analysis of boiler, turbine, and governor system, and the study of control algorithm are preceded. The thermal power plant is operated by various control systems. In the case of faulty governor system, it takes long days to solve the problem and impossible to repair the mechanism without outage. A non-planned out-age is taken into consideration because of economical power production. In this paper, to clear the continuous swings of an old turbine governor system(YEOSU #1), the trend, the control logic, and the hydraulic mechanism are analyzed, and then the control circuit with ADAPT function and the 1st order lag circuit are inserted and modified. After that, the power plant comes to automatic governor control operation.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2389-2391
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• 2000

To design high quality products at low cost is one of very important tasks for engineers. Design optimization for performances can be one solution in this task. There is the robust design which has been proved effectively in many fields of engineering design. In this paper, the concept of robust design is introduced and combined to the fuzzy optimization method and the fuzzy logic system method with non-singleton. These methods are applied for data analysis to get optimum parameters and to reduce experiments. The optimum parameter set points are obtained by the proposed methods. These methods are applied to a filter circuit, a part of the audio circuit of mobile radio transceiver. The simulation results are compared each other. The new methods reduce and predict the effect of parameter variation sources

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.45-54
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• 2004

Usually, according as accumulation degree of semi-conductor element increases, dynamic mistake test time increases sharply, and use of pattern generator is essential at manufacturing process to solve these problem. In this paper, we designed the PLD(Programmable Logic Device) circuit of pattern generator to examine dynamic mistake of semi-conductor element. Such all item got result that is worth verified action of return trip and function through simulation, and satisfy.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• The Transactions of the Korea Information Processing Society
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• v.4 no.4
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• pp.1004-1012
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• 1997

This paper proposes a new TRF(Transition Rise\Fall)delay model for the effcient hazard analysis in a 5-valued logic sumulation enviroment.For the hazzard for a given logic circuit, the timing analysis is first performed by means of a 5-valued logic simulator which uses the TRF delay model which incorporates the response delay for a reponse state with the transition delay for a transition state of an elment, and then hazards are detected through investigating timing relations.Simulation examples and experimental results are also given to demostrate the pradticability of the proposed methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.