• 한국정보통신학회논문지
• /
• 제9권3호
• /
• pp.582-586
• /
• 2005

본 논문은 locking 상태에 따라서 루프대역폭이 변화하는 Phase Locked Loop (PLL)의 구조를 제안하였다. 제안한 PLL은 기본적인 PLL 블록과 NOR Gate, Inverter, Capacitor, 그리고 Schmitt trigger로 이루어진 Locking Status Indicator(LSI) 블록으로 구성되었다. LSI는 Loop Fille.(LF)에 공급되는 전류와 저항 값을 locking 상태에 따라 변화시켜서 unlock이 되면 넓은 루프대역폭 가지는 PLL로, lock이 되면 좁은 루프대역폭을 가지는 PLL로 동작하도록 한다. 이러한 구조의 PLL은 짧은 locking 시간과 저 잡음의 특성을 동시에 만족시킬 수 있다. 제안된 PLL은 Hynix CMOS $0.35{\mu}m$ 공정으로 Hspice 시뮬레이션 하였으며 40us의 짧은 locking 시간과 -76.1dBc 크기의 spur를 가진다.

• 한국공작기계학회논문집
• /
• 제15권6호
• /
• pp.121-126
• /
• 2006

Snap-fit is being used in manufacture of plastic products. Integral features using snap-fit are classified as locks, locators and enhancements. Locking features complete the process of attachment by providing physical interference to prevent separation. Looking feature pairs consist of two components, i.e., a flexible latch and a rigid catch and require particular care and attention for their selection. We can make several locking feature pairs by selecting latch and catch, but some parts restrict freedom of selection. Therefore, part designers must know the characteristic properties of generic locking feature forms as considering a specific design problem. In this paper, it has been presented about problem of small size products using locking feature and then introduced new locking feature applicable to small parts.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.963-966
• /
• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.246-248
• /
• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• 한국기계가공학회지
• /
• 제19권8호
• /
• pp.28-34
• /
• 2020

In this study, hole-boss locking washers were developed to prevent vibrational loosening, and a benchmark test was conducted to compare these washers with existing wedge locking washers, which are imported and high-priced. The developed washers consist of an upper washer with bosses and a lower washer with holes, and the bosses are caught in the holes so that the bolt is not loosened. Additionally, the top side of the upper washer and the underside of the lower washer have small wedges perpendicular to the direction of the bolt loosening, suppressing slips. A test by the Korea Test Laboratory indicated that the ratio of the loosening torque to the joining torque is greater than 70%, confirming that the developed washers have a sufficiently high anti-loosening performance. A Junker test apparatus was manufactured for the testing of vibrational loosening and a test comparison between the proposed washers and the existing wedge locking washers shows that the proposed washers have a slower reduction in the clamping force and a higher loosening-resistance in a vibrational circumstance compared with the wedge locking washers. These results indicate that the developed washers demonstrate a high performance and boast price competitiveness.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.607-608
• /
• 2008

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.509-510
• /
• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2004년도 춘계학술대회
• /
• pp.728-732
• /
• 2004

In the FE analysis of sheet metal forming, efficient results can be obtained by using shell elements rather than using solid elements. However, shell elements have some limitations to describe three-dimensional material laws. In the recent years, solid-shell element, which has only translational degree of freedom like solid element, has been presented. The assumed nature strain (ANS) and enhanced assumed strain (EAS) methods can be used to remove several solid-shell locking problems. In this paper, ANS method was used for diminish transverse shear locking and EAS method for thickness locking. Using the element, the steel pipe making process from flat plate analyzed effectively, which is including bending and welding.

• 한국통신학회논문지
• /
• 제22권8호
• /
• pp.1622-1631
• /
• 1997

A 3-stages Active Microstrip Phased Array Antenn(AMPAA) is implemented using Injection-Locking Coupled Oscillators(ILCO). The AMPAA is a beam scanning active antenna with capability of electrical scanning by frequency varation of ILCO. The synchronization of resonance frequencies in array elements is occured by ILCO, and the ILCO amplifies the injection signal and functions as a phase shifter. The microstrip ptch is operated as a radiation element. The unilateral amplifier is a mutual coupling element of AMPAA, eliminates the reverse locking signal and controls the locking bandwidth of ILCO. The possibility of Monolithic Microwave Integrated Circuits(MMIC) of T/R module is proposed by simplified and integrated fabrication process of AMPAA. The 0.75.$lambda_{0}$ is fixed for a mutual coupling space to wide the scanning angle and minimize the multi-mode. The AMPAA has beam scanning angle of 31.4.deg., HPBW(Half Power Beam Widths) of 26.deg., directive gain of 13.64dB and side lobe of -16.5dB were measured, respectively.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.191-193
• /
• 2005

Flash memories are one of best media to support portable computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient data processing. F2PL improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process.