• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.29-34
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• 2007

This paper presents a novel photonic bandgap (PBG) structure for size reduction and linearity improvement in power amplifier. The proposed structure is a two-dimensional (2-D) periodic lattice patterned on a dielectric slab that does not require nonplanar fabrication process. Throughout the experi-mental results, this structure has more broad stopband and high suppression performance than conventional three cell PBG and distorted uniplanar compact-PBG (DUC-PBG). This new PBG structure can be applied with power amplifier for linearity improvement. The 3rd intermodulation distortion (IMD3) of the power amplifier using new PBG structure is -36.16 dBc for (code division multiple access) CDMA applications. Compared with power amplifier without the proposed PBG structure, improved IMD3 is -13.49 dBc.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.3
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• pp.524-530
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• 2011

This paper analyzes fault tolerance under a stator turn fault, according to the winding configuration. Improvement of torque characteristics and fault tolerance can be achieved by winding configuration without additional methods. And, torque characteristics and fault tolerance according to the winding configuration can be usually analyzed by analytical method. But, when the stator turn fault generates, compare to the steady-state, analysis of torque characteristics and fault tolerance using the analytical method is not accurate because it does not reflect influence in mutual inductance and magnetic non-linearity. Therefore, analysis of torque characteristics and fault tolerance has to be performed by using the numerical method under fault condition. This paper develops fault characteristics according to the winding configuration using the FEM-base model considered magnetic non-linearity. And, this paper suggests fault tolerance improvement according to the winding configuration, by the comparison of 8/12 and 10/12 models, under fault condition.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.124-128
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• 2006

In this paper, Compact Microstrip Resonant Cell(CMRC)s have been employed to suppress IMD(Intermodulation Distortion) of the 3-Way Doherty amplifier. This method can not only improve the linearity and the efficiency but also be simpler, smaller and more inexpensive than existing linearity methods; (for example harmonic feedback, back off, feed-forward, predistortion and so on) Also, using only one divider reduces the size of the proposed 3-Way Doherty amplifier. As a result, the IMD3 and the PAE have been improved by 4.5 dB and by $9.2\%$, respectively, using the proposed Doherty amplifier with CMRC.

• Journal of Advanced Navigation Technology
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• v.18 no.3
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• pp.229-235
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• 2014

This paper presents the Doherty power amplifier with a digitally controlled analog predistorter circuit of Scintera Corp. to produce high power efficiency and high linearity performance. The analog predistorter improves the linearity performance because of controlling amplitude and phase values of input signal in order to improve intermodulation performance of power amplifier. Also, the power amplifier is designed by the Doherty technology to obtain the high efficiency performance. To validate the Scintera's analog predistorter, we are implemented the power amplifier with Doherty method at center frequency 2150 MHz. Compared with the balanced amplifier, the power amplifier is improved above 11% enhanced efficiency and more than 15 dB ACPR improvement.

• Journal of electromagnetic engineering and science
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• v.7 no.2
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• pp.91-95
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• 2007

In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through $0.13{\mu}m$ RF CMOS process for WiBro system. The designed LNA achieves +7.8 dBm of input-referred 3^{rd}$-order intercept point (IIP3) with 13.2 dB of Power Gain, 1.3 dB of noise figure and 5.7mA @1.5V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 dB without degrading other features such as gain and noise figure.

• Journal of Biomedical Engineering Research
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• v.21 no.6
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• pp.583-589
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• 2000

본 논문에서는 핵자기공명영상의 고해상도를 이루고, 영상의 신뢰성을 높이기 위해서 선형성이 증가된 경사자기장 코일의 설계와 제작에 목적을 두었다. Maxwell pair를 이용하여 Z-경사자계의 선형성을 증강시키기 위해 코일의 기하학적인 형태의 이론적인 계산과 몇 가지 형태의 코일로부터 예상되는 자기장 및 경사자기장의 분포를 구현했다. 즉, 코일 축 방향의 자기장을 구면좌표계에서 전개하는 방법으로 Maxwell pair의 크기와 위치를 계산하고, 유한요소법을 이용하여 자기장 및 경사자기장의 2차원 분포를 그렸다. 더불어 이론적인 계산 결과와 함께 자기장의 2차원 분포를 토대로 실제 경사자기장 코일을 제작하였고 이를 0.15 Τ 핵자기공명영상기에 적용하여, 영상을 획득하였다. 기존의 방법에 따른 Maxwell pair 형태를 이용한 경우에 코일지름의 40% DSV(diameter spherical volume)내에서 DSV의 5% 이내의 뒤틀림(distortion)을 갖는 선형성이 유지되었고, 새롭게 시도된 방법에 의한 경사자기장 코일의 경우는 코일지름의 70% DSV 내에서 DSV의 5% 이내의 뒤틀림을 갖는 선형성을 유지하였으며, 설계 제작된 경사자기장 코일과 RF-코일을 이용하여 이를 확인하였다. 본 연구에서 제작된 경사자기장 코일의 선형성은 Maxwell pair 코일보다 향상된 결과를 보았으며, 본 논문에서 제시하는 방법은 자기공명영상의 해상도 향상에 기여할 것으로 판단된다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.2
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• pp.82-87
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• 2017

This paper presents performance improvement of CO gas sensor signal conditioner for early fire warning system. The warning system is based on the CO sensor and its advanced signal conditioning modules network that employ electochemical gas sensor. The electochemical has advantage of having a linear output and operating with a low consumption and fast response. This electrochemical gas sensor contains a gas membrane and three electrodes(working, counter, reference electrode) in contact with an electrolyte. To use a three-electrode sensor, a voltage has to be applied between the working and the reference electrode according to the specification of the sensor. In this paper, we designed these requirements that should be considered in temperature compensation algorithm and electrode measurement of CO sensor modules by using advanced signal conditioning method included 3-electrode. Simulation and experimental results show that signal conditioner of CO sensor module using 3-electrode have a advantage linearity, sensitivity and stability, fast response etc..

• Journal of Korean Institute of Industrial Engineers
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• v.3 no.2
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• pp.57-62
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• 1977

We consider the problem of determining the optimal replacement policy of the items which deteriorate appreciably with time and become obsolete. Most of the conventional engineering economy models including the widely-accepted MAPI model assume linearity of technological improvement over time, in obtaining the economic lives of items and the net present values of the replacement alternatives under consideration. The main achievement of this paper is in that it successfully relaxes this strict linearity assumption to accommodate various other types of technological improvements in determining those values. Based on these results, we also include in this paper the mathematical models by which to determine the optimal replacement policies of items both under and without capital budgeting constraints.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.