• Proceedings of the KIEE Conference
• /
• 2002.07b
• /
• pp.796-798
• /
• 2002

In these days, the interruption capability of some circuit breakers, which are installed in the transmission systems, is getting lower than the magnitude of the fault current because of continuous increase of power demand and relatively short power line which was installed in forms of mesh network As a result of these situations, fault current limiters (FCLs) are strongly necessary. There are various types which is investigated around the world, and new power apparatuses that have been newly considered and developed by many manufactures. In this paper, we considered resistive superconducting fault current limiters with YBCO thin films. The resistive limiters utilize a transition of YBCO films from superconducting to normal state caused by exceeding the critical current. By means of newly occurred impedance, the fault current will be limited effectively. Generally, a few current path patterns are available for YBCO films to enhance the current limiting performance of YBCO films. In this paper. the meander-type and the bi-spiral-type were used for current paths of YBCO flims. When YBCO films are quenched into the normal state, bubbles could be observed on the surface of YBCO films. Using our high-speed camera, the number of bubbles and the size of bubbles could be visualized and the relation between bubbles and current density was analyzed. By means of moving pictures of bubbles, we observed how the quench extended or how the heat was conducted in films.

• Journal of Electrical Engineering and Technology
• /
• v.3 no.3
• /
• pp.391-400
• /
• 2008

Multi-pulse topology of converters using elementary six-pulse GTO - VSC (gate turn off based voltage source converter) operated under fundamental frequency switching (FFS) control is widely adopted in high power rating static synchronous compensators (STATCOM). Practically, a 48-pulse ($6{\times}8$ pulse) configuration is used with the phase angle control algorithm employing proportional and integral (PI) control methodology. These kinds of controllers, for example the ${\pm}80MVAR$ compensator at Inuyama switching station, KEPCO, Japan, employs two stages of magnetics viz. intermediate transformers (as many as VSCs) and a main coupling transformer to minimize harmonics distortion in the line and to achieve a desired operational efficiency. The magnetic circuit needs altogether nine transformers of which eight are phase shifting transformers (PST) used in the intermediate stage, each rating equal to or more than one eighth of the compensator rating, and the other one is the main coupling transformer having a power rating equal to that of the compensator. In this paper, a two-level 48-pulse ${\pm}100MVAR$ STATCOM is proposed where eight, six-pulse GTO-VSC are employed and magnetics is simplified to single-stage using four transformers of which three are PSTs and the other is a normal transformer. Thus, it reduces the magnetics to half of the value needed in the commercially available compensator. By adopting the simple PI-controllers, the model is simulated in a MATLAB environment by SimPowerSystems toolbox for voltage regulation in the transmission system. The simulation results show that the THD levels in line voltage and current are well below the limiting values specified in the IEEE Std 519-1992 for harmonic control in electrical power systems. The controller performance is observed reasonably well during capacitive and inductive modes of operation.

• Journal of Satellite, Information and Communications
• /
• v.10 no.3
• /
• pp.26-31
• /
• 2015

This paper deals with a size-reduced Ku-band waveguide limiter. Basically, it passes the signal from 16.125 GHz through 16.375 GHz, but when excessively high power is injected to the input port, it should change to a bandstop filter. Furthermore, it is required to change to bring attenuation by more than 20 dB and 50 dB over a narrow band and the entire passband, respectively. Therefore, in order to meet this requirement, a limiting device is implemented with multiple PIN-diode posts that enable the limiter to be the bandpass filter and stopband one at the off and on states of the PIN-diode switch, respectively. So, the design goes through the equivalent circuit modelling and the geometry is realized in the accurate electromagnetic analysis CAD tool. Finally, the result is discussed to shed light on whether it complies with the aforementioned requirement.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.2
• /
• pp.262-267
• /
• 2011

In the power system, the transformer's neutral earth reactor line 1 grounding failure may occur. By limiting the magnitude of the failure grounding current flow, it will aid to reduce the failure of the transformer. Consequently, this also may avoid the failure of the disconnection of the industrial insulator line that cause by melting. Besides, utilizing the decreasing circuit breaker or others related equipment can use to avoid the possibility of explosion of the transformer. If the failure happen during the operation of the power system, a huge interference will definitely may occur. Therefore, by installing the DONGBUSAN S/S #3M.Tr neutral earth reactor among TOP and BOTTOM BRACE part in the power system, the causes of the rising temperature and reason of the over-current flow that cause by over-current can be analyze.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.3
• /
• pp.15-20
• /
• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

• International Journal of Highway Engineering
• /
• v.16 no.6
• /
• pp.51-57
• /
• 2014

PURPOSES : An conventional method for electric power generation is converting thermal energy into mechanical energy then to electrical energy. Due to environmental issues such as global warming related with $CO_2$ emission etc., were the limiting factor for the energy resources which resulting in extensive research and novel technologies are required to generate electric power. Thermal energy harvesting using thermoelectric generator is one of energy harvesting technologies due to diverse advantages for new green technology. This paper presents a possibility of application of the thermoelectric generator's application in the direct exchange of waste solar energy into electrical power in road space. METHODS : To measure generated electric power of the thermoelectric generator, data logger was adopted as function of experimental factors such as using cooling sink, connection methods etc. Also, the thermoelectric generator、s behavior at low ambient temperature was investigated as measurement of output voltage vs. elapsed times. RESULTS : A few temperature difference between top an bottom of the thermoelectric generator is generated electric voltage. Components of an electrical circuit can be connected in various ways. The two simplest of these are called series and parallel and occur so open. Series shows slightly better performance in this study. An installation of cooling sink in the thermoelectric generator system was enhanced the output of power voltage. CONCLUSIONS : In this paper, a basic concepts of thermoelectric power generation is presented and applications of the thermoelectric generator to waste solar energy in road is estimated for green energy harvesting technology. The possibility of usage of thermoelectric technology for road facilities was found under the ambient thermal gradient between two surfaces of the thermoelectric module. An experiment results provide a testimony of the feasibility of the proposed environmental energy harvesting technology on the road facilities.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.79-85
• /
• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.1297-1300
• /
• 2008

A conventional linear accelerator system requires a flat-topped pulse with less than ${\pm}$ 0.5% ripple to meet the beam energy spread requirements and to improve pulse efficiency of RF systems. A pulse transformer is one of main determinants on the output pulse voltage shape. The pulse transformer was investigated and analyzed with the pulse response characteristics using a simplified equivalent circuit model. The damping factor ${\sigma}$ must be >0.86 to limit the overshoot to less than 0.5% during the flat-top phase. The low leakage inductance and distributed capacitance are often limiting factors to obtain a fast rise time. These parameters are largely controlled by the physical geometry and winding configuration of the transformer. A rise time can be improved by reducing the number of turns, but it produces larger pulse droop and requires a larger core size. By tradeoffs among these parameters, the high-voltage pulse transformer with a pulse width of 10 ${\mu}s$, a rise time of 0.84 ${\mu}s$, and a pulse droop of 2.9% has been designed and fabricated to drive a klystron which has an output voltage of 284 kV, 30-MW peak and 60-kW average RF output power. This paper describes design optimization of a high-voltage pulse transformer for high-power pulsed applications. The experimental results were analyzed and compared with the design. The design and optimal tuning parameter of the system was identified using the model simulation.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1034-1035
• /
• 2015

Watertight 25.8 kV/600 A/12.5 kA fault current limiters (FCLs) have successfully installed in five areas (Incheon, Seoul, Gyeong-gi, Daejeon, Suwon) on KEPCO power distribution line for the purpose of commercial demonstrations. The fault current limiting operation of this FCL, which includes functions of sensing, commutation, and reduction of fault currents, is perfectly completed within 1 cycle immediately after fault occurs. The performance of FCL was verified by short circuit test, impedance test, insulation test, temperature-rise test, and control test, etc at PT&T in LS industrial systems, which is the official certification institute in Korea. In 2013, and also the FCL field test was performed in order to test the protection coordination between conventional relays and FCL, on the 1.5 kA and 5.0 kA faults, which were made by connecting the Artificial Fault Generator (AFG) to the distribution line in test grid at KEPCO Power Testing Center. The next step of this project is to check the FCL conditions caused by real external environment, and acquire the various data from five regions installed with FCL. In this paper, we intend to explain the FCL specifications and performance characteristics, and check the expected effect by application of FCL to power distribution line based on the power system analysis of an application site.

• Progress in Superconductivity
• /
• v.10 no.1
• /
• pp.60-67
• /
• 2008

We present domestic efforts for superconducting fault current limiter (SFCL) application in the Korea Electric Power Corporation (KEPCO) grid and pending points at issue. KEPCO's decision to upgrade the 154 kV/22.9 kV main transformer from 60 MVA to 100 MVA cast a problem of high fault current in the 22.9 kV distribution lines. The grid planners supported adopting an SFCL to control the fault current. This environment friendly to SFCL application must be highly dependent upon the successful development of SFCL having specifications that domestic utility required. The required conditions are (1) small size of not greater than twice of 22.9 kV gas insulated switch-gear (GIS), (2) sustainability of current limitation without the line breaking by circuit breakers (CB) for maximum 1.5 seconds. Also, optionally, recommended is (3) the reclosing capability. Conventional resistive SFCLs do not meet (1) $\sim$ (3) all together. A hybrid SFCL is an excellent solution to meet the conditions. The hybrid SFCL consists of HTS SFCL components for fault detection and line commutation, a fast switch (FS) to break the primary path, and a limiter. This characteristic structure not only enables excellent current limiting performances and the reclosing capability, but also allows drastic reduction of HTS volume and small size of the cryostat, resulting in economic feasibility and compactness of the equipment. External current limiter also enables long term limitation since it is far less sensitive to heat generation than HTS. Semi-active operation is another advantage of the hybrid structure. We will discuss more pending points at issues such as maintenance-free long term operation, small size to accommodate the in-house substation, passive and active control, back-up plans, diagnosis, and so on.