• Journal of the Korea Society of Computer and Information
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• v.24 no.4
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• pp.11-18
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• 2019

Previous mutual authentication schemes operate on the basis of validated cryptographic functions and hash functions, but these functions require a certain amount of memory capacity. However, since ultra-lightweight IoT devices have a very small amount of memory capacity, these functions can not be applied. In this paper, we first propose a text steganography communication scheme suitable for ultra-lightweight IoT devices with limited resources, and then propose a mutual authentication scheme based on the text steganography communication. The proposed scheme performs mutual authentication and integrity verification using very small amount of memory. For evaluation, we implemented the proposed scheme on Arduino boards and confirmed that the proposed scheme performs well the mutual authentication and the integrity verification functions.

• Journal of IKEEE
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• v.25 no.2
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• pp.309-314
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• 2021

The proposed preamplifier for the static random access memory reduces the time required for the sense amplifier enable during the read operation by 55%, which leads to a significant speed up the total spped. This is attirbuted to the novel circuit techqniue that cancels out the transistor mismatch which is induced by the process variation. In addition, a selective enable circuit for preamplifier circuit is proposed, so the proposed preamplifier is enabled only when it is required. Accordingly the energy overhead is limited below 4.45%.

• KEPCO Journal on Electric Power and Energy
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• v.8 no.2
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• pp.93-96
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• 2022

The boiler tubes of thermal power plants are exposed to harsh environment of high temperature and high pressure, and the deterioration state of materials rapidly increases. In particular, parent material and welds of the materials used are subjected to a temperature change and various constraints, resulting in deformation and its growth, resulting in frequent leakage accidents caused by tube failure. The power plant checks the integrity of boiler tubes through non-destructive testing as it may act as huge costs loss and limitation of power supply during power station shutdown period due to boiler tube leakage. However, the current non-destructive testing is extremely limited in the field to detect micro cracks. In this study, the ability of metal magnetic memory technique to detect flaws of size that are difficult to inspect by the visual or general non-destructive methods was verified in the early stage of their occurrence.

• ETRI Journal
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• v.45 no.6
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• pp.1035-1045
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• 2023

We propose a novel graphics processing unit (GPU) algorithm that can handle a large-scale 3D fast Fourier transform (i.e., 3D-FFT) problem whose data size is larger than the GPU's memory. A 1D FFT-based 3D-FFT computational approach is used to solve the limited device memory issue. Moreover, to reduce the communication overhead between the CPU and GPU, we propose a 3D data-transposition method that converts the target 1D vector into a contiguous memory layout and improves data transfer efficiency. The transposed data are communicated between the host and device memories efficiently through the pinned buffer and multiple streams. We apply our method to various large-scale benchmarks and compare its performance with the state-of-the-art multicore CPU FFT library (i.e., fastest Fourier transform in the West [FFTW]) and a prior GPU-based 3D-FFT algorithm. Our method achieves a higher performance (up to 2.89 times) than FFTW; it yields more performance gaps as the data size increases. The performance of the prior GPU algorithm decreases considerably in massive-scale problems, whereas our method's performance is stable.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.1-10
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• 2010

As processor platforms are continuously moving toward wireless mobile systems, embedded mobile processors are expected to perform more and more powerful, and therefore the development of an efficient power management algorithm for these battery-operated mobile and handheld systems has become a critical challenge. It is well known that a memory system is a main performance limiter in the processor point of view. Although many DVFS studies have been considered for the efficient utilization of limited battery resources, recent works do not explicitly show the interaction between the processor and the memory. In this research, to properly reflect short/long-term memory access patterns of the embedded workloads in wireless mobile processors, we propose a memory buffer utilization as a new index of DVFS level prediction. The simulation results show that our solution provides 5.86% energy saving compared to the existing DVFS policy in case of memory intensive applications, and it provides 3.60% energy saving on average.

• The Journal of Korean Medicine
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• v.29 no.5
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• pp.67-76
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• 2008

Objectives : Amnesia is theloss or impairment of memory, caused by physical injury, disease, drugs, or emotional trauma. Recently, the average life span is increasing, while at the same time, the incidence of dementia-like diseases in conjunction with amnesia are also increasing. Therefore learning and memory are very important issues in modern society. Ancient Korean physicians used several herbs to treat dementia and these herbal effects were described in Korean herbal books. Among them are some reports on several cognitive-enhancing herbs which have since been shown to improve dementia in recent pharmacological studies, such as Panax ginseng; however, the facilitatory effects of many Korean cognitive-enhancing herbs on learning and memory are limited. Learning and memory are essential requirements for every living organism in order to cope with environmental demands; cholinergic systems are known to be involved in learning and memory. Methods : In this study, the effects of Acori graminei rhizoma (AGR, 石菖蒲) on learning and memory were investigated by Morris water maze, eight-arm radial maze, and the effects on the central cholinergic system of rats injected with scopolamine. Results : In the water maze, the experimental animals were trained to find a platform in a fixed position for 6 days and then received a 60 sec probe trial in which the platform was removed from the pool on the 7th day. In the eight-arm radial maze, the animals were tested four times per day for 6 days. Scopolamine impaired performance of the maze tests and reduced activity of acetylcholinesterase (AchE) in the hippocampus, which is a marker for the central cholinergic system. There were significant reversals from the scopolamine-induced deficits on learning and memory in these tests, through daily administrations of AGR (100 mg/kg, p.o.) over 14 consecutive days. These treatments also reduced the loss of cholinergic activity in the hippocampus induced by scopolamine. Conclusions : These results demonstrated that AGR ameliorated learning and memory deficits by affecting the central acetylcholine system.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.470-472
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• 1987

This paper deals with the continuous-discrete estimation problem using FIR filters and performs modeling error analyses of the FIR filters, compared to Kalman filter and the limited memory filters, via computer simulations. It is shown that, the less driving noise the system has, the better performance the FIR filter exhibits and that this characteristic appears rare distinctly in nonlinear system than in linear systems.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.476-487
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• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.5 s.108
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• pp.408-415
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• 2006

This paper suggests an improved system-level model of RF power amplifiers(PAs) including memory effects, and validates the suggested model by analyzing the power spectral density of the output signal with a predistortion linearizer. The original three-box(Wiener-Hammerstein) model uses input and output filters to capture RF frequency response of PAs. The adjacent spectral regrowth that occurs in three-box model can be perfectly removed by Hammerstein structure predistorter. However, the predistorter based on Hammerstein structure achieves limited performance in real PA applications due to other memory effects except RF frequency response. The spectrum of the output signal can be predicted accurately using the suggested model that changes a memoryless block in a three-box model with a memory polynomial. The proposed model accurately predicts the output spectrum density of PA with Hammerstein structure predistorter with less than 2 dB errors over ${\pm}30$ MHz adjacent channel ranges for IEEE 802.11 g WLAN signal.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.75-81
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• 2014

The integral image is the sum of input image pixel values. It is mainly used to speed up processing of a box filter operation, such as Haar-like features. However, large memory for integral image data can be an obstacle on an embedded hardware environment with limited memory resources. Therefore, an efficient method to store the integral image is necessary. In this paper, we propose a memory size reduction hardware design for integral image. The hardware design is used two methods. It is the new integral image memory and modulo calculation for reducing integral image data. The new integral image memory has additional calculation overhead, but it is not obstacle in hardware environment that parallel processing is possible. In the Xilinx Virtex5-LX330T targeted experimental result, integral image memory can be reduced by 50% on a $640{\times}480$ 8-bit gray-scale input image.