• 예술인문사회 융합 멀티미디어 논문지
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• 제8권11호
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• pp.523-530
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• 2018

전력 변환 시스템의 고효율, 고전력 밀도를 위한 많은 연구가 활발하게 되어 왔다. 스위칭 주파수를 높임으로써 컨버터의 소형화 및 경량화를 꾀할 수 있으나 스위칭 주파수를 높이게 되면 스위칭 손실이 증가하게 된다. 따라서 스위칭 손실을 저감하기 위한 기법이 적용되어야 한다. 본 연구에서는 이 중 부가적인 회로 없이 변압기의 누설 인덕턴스와 스위치의 출력 커패시터를 이용하여 영전압 스위칭이 가능한 영전압 스위칭(Zero-Voltage Switching) 위상천이(Phase Shift) 풀 브리지 컨버터를 이용하여, 영전압 위상천이 풀 브리지 컨버터의 동작원리를 해석하고 2kW의 출력을 갖는 영전압 스위칭 풀 브리지 컨버터를 설계한다. 각 모드별 동작을 스위치 도통 상태와 전압 전류 파형으로 분석하였다. 분석 결과, 영전압 스위칭이 도통 스위치들의 각 쌍 사이의 위상 변화에 의해 최대 효율을 달성하는 것을 확인하였다. 제안된 영전압 위상천이 풀 브리지 컨버터 설계를 검증하기 위해 컴퓨터 시뮬레이션 툴인 PowerSIM사의 PSIM을 이용하여 설계된 2kW 출력 전력을 갖는 영전압 스위칭 위상천이 풀 브리지 컨버터의 성능을 확인하였고, 실험을 통해 연구의 타당성을 입증하였다.

• 전력전자학회논문지
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• 제10권3호
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• pp.257-263
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• 2005

발전기의 회전자 권선의 층간단락이 발생하면 자속의 불평형과 비대칭적인 발열로 인한 불안정한 진동이 발생하게 된다. 이러한 층간단락으로 발생될 수 있는 심각한 사고를 방지하기 위하여 회전자 권선의 층간단락 진단기법에 관한 연구는 매우 중요하다. 현재 운전중 진단기법이 주로 사용되고 있는 센서부착방식의 단점을 개선하기 위해 본 논문에서는 발전기의 계자 층간단락을 검출할 수 있는 새로운 센서없는 방법을 제안하였고 제안된 방식에서는 발전기에서의 전압 및 전류의 측정값만으로 단락현상을 판단할 수 있도록 하였다. 제안된 방식의 적용 가능성을 검토하기 위해 디지털 시뮬레이션을 통해 공극자속밀도, 누설자속, 발전된 전압 및 단락계자전류 등과 관련된 특성을 이론적으로 분석함으로써 단락 판정을 위한 근거를 제시하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.10-10
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• 2009

Transparent BNO thin films were grown on Al-doped ZnO (AZO)/Ag/AZO/polyethersulfon (PES) (abbreviated as AAAP) transparent electrodes at a low temperature by the NCD technique. The BNO films grown on the crystallized AZO/Ag/AZO (AAA) electrodes exhibit an amorphous phase with a root mean square (rms) roughness of approximately 2 nm in the range of deposition temperature. The capacitors (Pt/BNO/AAAP) with BNO films grown at $100^{\circ}C$ show a dielectric constant of 24 and dissipation factor of 8% at 100 kHz, a leakage current density of about $8{\times}10^{-6}A/cm^2$ at an applied voltage of 1.0V. The optical transmittances of the BNO/AAAP exhibited above 80% at wavelength of 550nm at all of deposition temperature. The mechanical stability of the BNO/AAA as well as AAA electrode with the PES substrates through the bending was ensured for flexible electronic device applications. The transparent BNO capacitors grown on AAAP are powerful candidate for integration with the transparent solar cells.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.28-31
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• 2000

In this paper, the effects of La addition of PLZT(x/30/70) thin films Prepared by sol-gel method are investigated for NVFRAM application. The tetragonality (c/a), the grain size, and the surface roughness of PLZT thin films decrease with an increase of La concentration. As the La concentration increases, the dielectric constants at 10 kHz increase from 450 to 600, while the loss tangent decrease from 0.075 to 0.025. Also, the leakage current density at 100kV/cm decrease from 5.83$\times$10$^{-7}$ to 1.38$\times$10$^{-7}$ 4/$\textrm{cm}^2$. In the results of hysteresis loops measured at $\pm$170kV/cm, the remanent polarization and the coercive field of PLZT thin films with La concentration from 0 to 10㏖％ decrease from 20.8 to 10.5 $\mu$C/cm and from 54.48 to 32.12kV/cm, respectively. After a fatigue measurement by applying 10$^{9}$ square pulses with $\pm$5V, the remanent polarizations of PLZT thin films with 0 and 10㏖％ La concentration decrease about 64 and 42 ％ from initial state. In the results of retention measurement after 10$^{5}$ s, PLZT thin films with 0 to 10mo1％ La concentration show that the remanent polarization is decreased about 43％ and 9％ from initial state, respectively.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.63.1-63
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• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• 한국세라믹학회지
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• 제40권4호
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• pp.398-400
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• 2003

The YMnO$_3$ thin films were prepared on platinized-silicon substrates by chemical solution deposition and annealed at 750 to 85$0^{\circ}C$ for 1 h under various oxygen pressures, from 2 mTorr to 760 Torr. Effects of annealing oxygen pressures on the crystallization behavior and electrical properties of YMnO$_3$ thin films were investigated. Crystallinity and c-axis preferred orientation of YMnO$_3$ thin film were improved by decreasing the oxygen pressure but were deteriorated at extremely low oxygen pressure, 2 mTorr. Leakage current density of the YMn03 thin film decreased as the oxygen pressure decreased. The film annealed at 80$0^{\circ}C$ under 2 Torr, which had the best crystallinity and the highest c-axis preferred orientation. showed the best-developed ferroelectric C-V hysteresis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 합동춘계학술대회 논문집 전기물성,응용부문
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• pp.169-170
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• 2008

The heterolayered PZT/PT thick films were fabricated by two different methods - thick films of the PZT by screen printing method on alumina substrates electrodes with Pt, thin films of $PbTiO_3$ by the spin coating method on the PZT thick films and once more thick films of the PZT by the screen printing method on the $BaTiO_3$ layer The structural and the dielectric properties were investigated for effect of various stacking sequence of sol-gel prepared $PbTiO_3$ coating solution at interface of the PZT thick films. The insertion of $PbTiO_3$ interlayer yielded the PZT thick films with homogeneous and dense grain structure with the number of $PbTiO_3$ layers. The leakage current density of the PZT/$PbTiO_3-1$ film is less that $4.41{\times}10^{-9}\;A/cm^2$ at 5 V.