• Journal of Satellite, Information and Communications
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• v.9 no.3
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• pp.15-21
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• 2014

An electrostatic discharge (ESD) protection device, so called, N-type embedded silicon controlled rectifier (NESCR), was analyzed for high voltage operating I/O applications. A conventional NESCR standard device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, our modified NESCR_CPS_PPW device with proper junction/channel engineering such as counter pocket source (CPS) and partial P-well structure demonstrates highly latch-up immune current-voltage characteristics with high snapback holding voltage and on-resistance.

• Journal of IKEEE
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• v.15 no.2
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• pp.164-170
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• 2011

In this paper, we present a novel Lateral Insulated-Gate Bipolar Transistor(LIGBT) structure. The proposed structure has extra emitter between emitter and collector of the conventional structure. The added emitter can significantly improve latch-up current densities, forward voltage drop (Vce,sat) and turn-off characteristics. From the simulation results, the proposed LIGBT has the lower forward voltage drop(1.05V), the higher latch-up current densities($2.5{\times}10^3\;A/{\mu}m^2$), and the shorter turn-off time(7.4us) than those of the conventional LIGBT.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.27-32
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• 2016

A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.267-270
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10$\mu\textrm{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sifted conventional LTIGBT and the conventional LTIGBT which has the width of 17$\mu\textrm{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17$\mu\textrm{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field in the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.99-104
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• 2002

lateral insulated gate bipolar transistors(LIGBTs) are extensively used in high voltage power IC application due to their low forward voltage drops. One of the main disadvantages of the LIGBT is its scow switching speed when compared to the LDMOSFET. And the LIGBT with reverse channel structure is lower current capability than the conventional LIGBT at the forward conduction mode. In this paper, the LIGBT which included p+ ring and p-channel gate is presented at the reverie channel structure. The presented LIGBT structure is proposed to suppress the latch up, efficiently and to improve the turn off time. It is shown to improve the current capability too. It is verified 2-D simulator, MEDICI. It is shown that the latch up current of new LIGBT is 10 times than that of the conventional LIGBT Additionally, it is shown that the turn off characteristics of the proposed LIGBT is i times than that of the conventional LIGBT. It is net presented the tail current of turn off characteristics at the proposed structure. And the presented LIGBT is not n+ buffer layer because it includes p channel gate and p+ ring.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.45-53
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• 2013

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.15-18
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.