• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1292-1297
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• 1997

본 연구에서는 latch-up 개선책의 일환으로 개발중인 매립층을 갖는 retrograde well의 형성기술과 더불어 공정 단순화를 목적으로 개발된 BILLI (Buried Implanted Layer for Lateral Isolation) well 구조[1]에 대한 공정 유기 결함을 분석하고 그에 의한 소자 열화 특성을 분석 하였으며 그 개선책을 제시 하고자 하였다. 매립층 형성에 의한 유기결함은 접합 누설전류와 Gate oxide 신뢰성을 열화 시켰으나 이온주입 후 $1000^{\circ}C$ 이상의 온도에서 10sec 정도의 RTP anneal에 의해 그 소자 특성이 개선되며 표면 결함이 감소함을 알 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.833-836
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• 2007

A low power and small area source driver using LTPS TFTs is proposed for mobile applications. This source driver adopts level shifter with holding latch function and new R-to-R type digital-to-analog converter (DAC). The power consumption and layout area of the proposed source driver are reduced by 23% and 25% for 16M colors and qVGA AM-OLED panel, respectively.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.33-37
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• 2001

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.230-234
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• 1996

A new trenched Hybrid Schottky INjection Field Effect Transistor (HSINFET) is proposed and verified by 2-D semiconductor device simulation. The feature of the proposed structure is that the hybrid Schottky injector is implemented at the trench sidewall and p-n junction injector at the upper sidewall and bottom of a trench. Two-dimensional simulation has been performed to compare the new HSINFET with the SINFET, conventional HSINFET and lateral insulated gate bipolar transistor(LIGBT). The numerical results shows that the current handling capability of the proposed HSINFET is significantly increased without sacrificing turn-off characteristics. The proposed HSINFET exhibits higher latch-up current density and much faster switching speed than the lateral IGBT. The forward voltage drop of the proposed HSINFET is 0.4 V lower than that of the conventional HSINFET and the turn-off time of the trenched HSINFET is much smaller than that of LIGBT.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.61-63
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• 1987

In this paper, we develope a system which can perform signal processing for bar-code laser scanner. This system is composed of optical detector and preprocessor. The former detects the diffused light and converts it into TTL lebel output. The latter discriminator valid data from various raw data and transmits data to micro-processor. The preprocessor consists of edge transition detector, latch signal generator, module counter, register array, adder array, and buffer memory control circuit etc..

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.16-19
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• 2000

Power transistors to be used in Power Integrated Circuits(PIC) are required to have low on resistance, fast switching speed, and high breakdown voltage. The lateral IGBTs(LIGBTs)are promising power devices for high voltage PIC applications, because of its superior device characteristics. In this paper, dual cathode LIGBT(DCIGBT) for high voltage is presented. We have verified the effectiveness of high blocking voltage in the new device by using two dimensional devices simulator. We have analyzed the forward blocking characteristics , the latch up performance and turn off characteristics of the proposed structure. Specially, we have focused forward blocking of LIGBT. The forward blocking voltage of conventional LIGBT and the proposed LIGBT are 120V and 165V, respectively. . The forward blocking characteristics of the proposed LIGBT is better than that of the conventional LIGBT. This forward blocking comparison exhibits a 1.5 times improvement in the proposed LIGBT.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.17-19
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• 2004

트렌치 게이트 구조를 통해 순방향 전압 강하 손실 없이 기생 사이리스터 래치-업을 억제시키는 새로운 수평형 절연 게이트 바이폴라 트랜지스터 (LIGBT)를 제안하였다. 제안된 소자의 베이스 션트 저항은 정공의 우회로 인하여 감소하였으며, 이에 따라 기생 사이리스터 래치-업이 억제되었다. 제안된 소자의 순방향 전압강하는 트렌치 구조에 의한 유효 채널 폭 증가로 감소하였다. 제안된 소자의 동작 원리 분석을 위해 ISE-TCAD를 이용한 3차원 시뮬레이션을 수행하였으며, 표준 CMOS 공정을 이용하여 소자를 제작 및 측정하였다. 제안된 소자의 순방향 전압 강하는 기존의 LIGBT에 비해 증가하지 않았으며, 래치-업 용량은 2배로 향상되었다. 제안된 소자의 포화 전류는 감소하였으며, 이로 인하여 소자의 강인성 (ruggedness)이 향상되었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.520-524
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• 2017

Electrical relay in an essential part of smart grids, electrical vehicles, and LED lightning systems. Therefore, studying relay reliability is important. Relays using permanent magnet actuators (PMAs), which are energy efficient, are also in the spotlight. However, most of the permanent magnets used in PMAs have a characteristic wherein the magnetic flux decreases as the temperature increases. When the magnetic flux is reduced, the force acting on the actuator is reduced. Therefore, in this study, we measured the decrease in the relay operating speed with permanent magnet reduction due to temperature rise. In addition, changes in the bouncing phenomena due to magnetic flux reduction were analyzed. As a result, the operating speed of the relay has decreased and the bouncing phenomenon has not significantly changed.