• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.469-472
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• 2004

In this paper a current mode sense amplifier suitable for 30nm SONOS flash memories read operation is presented. The proposed sense amplifier employs cross coupled latch type circuit and current mirror to amplify signal from selected memory cell. This sense amplifier provides fast response in low voltage and low current dissipation. Simulation results show the sensing delay time and current dissipation for power supply voltages Vdd to expose limitations of the sense amplifier in various operating conditions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.26-33
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• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.474-477
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• 2004

This paper deals with a design experience of Control Element Drive Mechanism (CEDM) that is used to withdraw or insert control rods in nuclear reactor. The design is carried out to satisfy the performance requirements for CEDM that were given to ensure reliable and secure actions of the rods. The electrical parameters for four coils that energize the mechanical actuators in CEDM are determined first, Then a computer simulation for CEDM with these coils is performed to see how it works. An adjustment of the coil parameters is made from the simulation results. Finally, it is shown that our final design is valid to guarantee the required performance since the FEM(finite Element Method) calculation shows sufficient vertical attraction forces of a lift armature and a latch magnet, and good dynamics with a full load.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.1
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.4
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• pp.756-762
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• 2009

This paper proposes a high efficient Dual Buck Inverter design with a zero voltage switching (ZVS) control technique. The ZVS control is realized by adding a feedback loop circuit which is implemented by simple RS latch and TTL gate. The used load was 200W -Ceramic Metal Halide Lamp. The experimental results show that the proposed Inverter system could avoid the acoustic resonance and achieve high efficiency by Zero Voltage Switching.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.187-192
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• 2012

Development of new efficient, high voltage switching devices with wide safe operating area and low on-state losses has received considerable attention in recent years. One of those structures with a very effective geometrical design is the trench gate Insulated Gate Bipolar Transistor(IGBT).power IGBT devices are optimized for high-voltage low-power design, decided to aim. Class 1,200 V NPT Planer IGBT, 1,200 V NPT Trench IGBT for class has been studied.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1085-1088
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• 2007

A new DC-DC converter was designed for gate driver circuit using low temperature poly-Si TFT technology. To achieve high efficiency and small area, we proposed a cross-coupled type DC-DC converter which converts 5V of input voltage to 9V of output voltage and supplies 120$\mu$A of current to load. Its efficiency is 92.9% and the area is reduced as much as 19% compared to the previously reported latch type DC-DC converter.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.606-608
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• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.440-443
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• 2004

As a main management unit of MSC, PMU controls the MSC payload operation by issuing commands to other subunit and PMU internal modules. One of these main control functions is to drive the APS(Antenna Pointing System) when APS motion is required. For this purpose, SBC(Single Board Computer) for calculating motor commands and APDE for driving APM(Antenna Pointing Mechanism) by PWM signal operate inside PUM. In this paper, details on APDE design shall be described such as electronic board architecture, primary and redundant design concept, Cross-Strap, FPGA contents and latch-up immune concept, etc., which shall show good practices of electronic board design for space program.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.347-350
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• 1998

차세대 CMOS 구조에서 래치업 최소화를 위하여 고에너지 이온주입을 이용한 retrograde well 과 매몰층의 최적 공정 설계 변수 값들을 설정하였다. 본 논문에서는 두 가지의 모듸 모델 구조를 제안하고 silvaco 틀에 의한 시뮬레이션 결과를 비교 분석하엿다. 첫 번째 모델은 매몰층과 retrograde well을 조합한 구조이며, p+ injection trigger current가 600.mu.A/.mu.m 이상의 결과를 얻었고, 두번째 모델은 twin retrograde well을 이용하여 p+ injection 유지전류가 2500.mu.A/.mu.m이상의 결과를 얻었다. 시뮬레이션 결과, 두 모델 모두 도즈량이 많을수록 래치업 면역 특성이 좋아짐을 보았다. 시뮬레이션 조건에서 두 모델 모두 n+/p+ 간격은 2..mu.m 로 고정하였다.