• Analytical Science and Technology
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• v.7 no.3
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• pp.253-260
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• 1994

Analytical characteristics of low power-low flow inductively coupled plasma-atomic emission spectometry(ICP-AES) has been studied. Although the net intensity of the low power ICP is lower than the moderate power ICP, the signal to background ratio becomes higher since the background intensity decreases with decreasing the RF power. The detection limit of the low power ICP is comparable with that of the moderate power ICP. The dynamic range of the calibration curve of the low power ICP is $10^4{\sim}10^5$. The ionization interferences by alkali metals increase with increasing the carrier gas flow rate, but the effects are not varied significantly with the RF power.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• The Journal of Korean Physical Therapy
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• v.11 no.1
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• pp.71-77
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• 1999

The purpose of this study was to investigate the changes of muscle power by transcutaneous electrical nerve stimulation(TBNS), low frequency-low intensity(20pps, invisible muscle contraction intensity), low frequency-high intensity(20pps, visible muscle contraction), high frequency-low intensity(100pps, invisible muscle contraction intensity) and high frequency-high intensity(100pps, visible muscle contraction). The results were as follows. 1. Increased muscle power after 30 minutes of treatment by low frequency-low intensity TENS, and post-treatment 30 minutes muscle power were increased more than pre-treatment power(p<0.05). 2. Decreased muscle power after a 30 minute treatment by low frequency-high intensity TENS, and after the 30 minute treatment was terminated muscle power didn't recover to pre-treatment levels. 3. Decreased muscle power after 30 minute treatment by high frequency-low intensity TENS, but post-treatment 30 minute, muscle power didn't recover to pre-treatment levels. 4. The muscle power was remarkably decreased by high frequency-high intensity TENS after 30 minute treatment, in addition treatment terminated after 30minutes didn,t recover to pre-treatment power(p<0.05). 5. Lower frequency-low intensity TENS are good methods for preventing muscle fatigue, buty high intensity (TENS) are increased muscle fatigue. 6. Traditional TENS by high frequency-low intensity is a good method for preventing muscle fatigue.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• Journal of Digital Contents Society
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• v.15 no.3
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• pp.433-438
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• 2014

In this paper, we proposed the low power algorithm consider the battery and the task. The proposed algorithm setting the power consumption of unit time consider the capacity of the battery and the target time. Calculate the power consumption of all tasks. Calculate the average power consumption by the task have maximum power consumption and the task have minimum power consumption. Recalculate average power consumption consider the unit time of task. Compare calculated average power consumption and average power consumption of task. Compared results, low power algorithm processing the average power consumption less than or equal calculated power consumption of task. Low-power algorithm is greater than the average power consumption of the task to perform targeted tasks. Low-power processors and the task by dividing the power consumption of the device in large part for the low-power consumption is performed. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.479-481
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• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.713-719
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of Information Display
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• v.11 no.1
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• pp.21-23
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• 2010

A new level shifter using low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) for low-power applications is proposed. The proposed level shifter uses a capacitive-coupling effect and can reduce the power consumption owing to its no-short-circuit current. Its power saving over the conventional level shifter is 72% for a 3.3 V input and a 10 V output.