• Title/Summary/Keyword: LNA(Low Noise Amplifier)

Search Result 259, Processing Time 0.027 seconds

Post-Linearization Technique of CMOS Cascode Low Noise Amplifier Using Dual Common Gate FETs (두 개의 공통 게이트 FET를 이용한 캐스코드형 CMOS 저잡음 증폭기의 후치 선형화 기법)

  • Huang, Guo-Chi;Kim, Tae-Sung;Kim, Seong-Kyun;Kim, Byung-Sung
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.44 no.7 s.361
    • /
    • pp.41-46
    • /
    • 2007
  • A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

W-band Single-chip Receiver MMIC for FMCW Radar (FMCW 레이더용 W-대역 단일칩 수신기 MMIC)

  • Lee, Seokchul;Kim, Youngmin;Lee, Sangho;Lee, Kihong;Kim, Wansik;Jeong, Jinho;Kwon, Youngwoo
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.49 no.10
    • /
    • pp.159-168
    • /
    • 2012
  • In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

Review on RF Performance of Ultra Wide Band Device

  • Lee, Il-Kyoo;Kang, Bub-Joo
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.21 no.2
    • /
    • pp.34-39
    • /
    • 2007
  • UWB(Ultra Wide Band) system for high speed and high accurate location has been studying actively. This paper presents the design and implementation of RF transceiver for DS-CDMA(Direct Sequence-Code Division Multiple Access) UWB device. Major components of RF transceiver such as Low Noise Amplifier(LNA) and Band Pass Filter(BPF) are designed and then fabricated to meet wideband characteristics. The RF transceiver was implemented by the use of the fabricated components and commercial devices after carrying out performance simulation. Through the performance evaluation of the UWB RF transceiver with W-CDMA signal, the approach of design, implementation and evaluation of RF transceiver which is available to DS-CDMA UWB system is verified.

A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems

  • Park, Bong-Hyuk;Lee, Kyung-Ai;Hong, Song-Cheol;Choi, Sang-Sung
    • ETRI Journal
    • /
    • v.29 no.4
    • /
    • pp.421-429
    • /
    • 2007
  • This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

  • PDF

Performance Analysis of GPS Antenna for KSLV-I under Hot Temperature Environment (고온 환경에서 KSLV-I 발사체용 GPS 안테나의 성능 분석)

  • Moon, Ji-Hyeon;Kwon, Byung-Moon;Choi, Hyung-Don;Jung, Ho-Rac
    • Aerospace Engineering and Technology
    • /
    • v.6 no.1
    • /
    • pp.157-164
    • /
    • 2007
  • For a GPS antenna to normally receive GPS satellite signals during full flight mission of a satellite launch vehicle, it should be installed on skin of the vehicle. The surface of a launch vehicle is drastically heated up due to aerodynamic heating effect during flight, so that the GPS antenna mounted on surface of the launch vehicle is directly exposed to extremely hot temperature environment. Hot temperature test specification of the GPS antenna, therefore, is severer than inner components. This paper describes that procedures and results of performance analysis of the GPS antenna for KSLV-I under hot temperature environment. The GPS antenna was not deformed physically and inner LNA(Low Noise Amplifier) operated normally without performance degradation.

  • PDF

A Study on the Estimation of the Call Drop Rate for Call Admission Control in DS-CDMA Reverse Link (DS-CDMA 역방향 링크에서 호수락 제어를 위한 호 절단률 추정에 관한 연구)

  • 백진현;박용완
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.26 no.12B
    • /
    • pp.1677-1685
    • /
    • 2001
  • In this paper, we propose a call admission control scheme that can be performed within guaranteeing of required QoS(Quality of Services) in DS-CDMA(Direct Sequence-Code Division Multiple Access) reverse link. It has been performed rely on a physical channel numberonly and based on quality of received signal from MODEM(modulator/demodulator) part in established study. In other methods, the standard for services would have been set from statistical analysis of users\` location and using received power level in BTS(Base Transceiver Station). These ways bring about not only system loads but time delay or great differences from real environment. To solve these problems, we propose a call drop rate estimation algorithm for the purpose of call admission control based on measured value at LNA(Low Noise Amplifier) ports of BTS(Base Transceiver Station) in real time. This method proposed in this paper estimates a quality of offered service in real time, reduce system loads and shorten time delay which is needed to determine the standard for call admission control. But it requires a additional 17W complexity which can measure received signal power in BTS and estimate call drop rate.

  • PDF

Design and Fabrication of K-band multi-channel receiver for short-range RADAR (근거리 레이더용 K대역 다채널 전단 수신기 설계 및 제작)

  • Kim, Sang-Il;Lee, Seung-Jun;Lee, Jung-Soo;Lee, Bok-Hyung
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.37 no.7A
    • /
    • pp.545-551
    • /
    • 2012
  • In this paper, K-band multi-channel receiver was designed and fabricated for low noise amplification and down conversion to L-band. The fabricated multi-channel receiver incorporates GaAs-HEMT LNA(Low noise amplifier) which provides less than a 2 dB noise figure, IR(Image Rejection) Filter for rejection of image frequency, IR(Image rejection) mixer to reject a image frequency and improve an IMD(Intermodulation Distortion) characteristic. Test results of the fabricated multi-channel receiver show less than a 3.8 dB noise figure, conversion gain of more than 27dB, and IP1dB(Input 1dB Gain Compression Point) of -9.5 dB and over.

High performance V-Band Downconverter Module (V-band MMIC Downconverter 개발에 관한 연구)

  • 김동기;이상효;김정현;김성호;정진호;전문석;권영우;백창욱;김년태
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.27 no.5C
    • /
    • pp.522-529
    • /
    • 2002
  • MMIC circuits in whole receiver system was fabricated based on GaAs pHEMT technology. And a V-band downconverter module was fabricated by integrating these circuits. The downconverter module consists of a LO drive power amplifier which generates 24dBm output power, a low noise amplifier(LNA) which shows 20 dB small signal gain, an active parallel feedback oscillator which generates 1.6 dBm output power, and a cascode mixer which shows over 6dB conversion gain. The good conversion gain performance of our mixer made no need to attach any IF amplifier which grows conversion gain. Measured results of the complete downconverter show a conversion gain of over 20 dB between 57.5 GHz and 61.7GHz without IF amplifier.

Digital Control Unit Design for Power Amplifier Performance Improvement (전력증폭기 성능개선을 위한 디지털 제어장치 설계)

  • Lee, Byung-Sun;Roh, Hee-Jung
    • 전자공학회논문지 IE
    • /
    • v.47 no.4
    • /
    • pp.34-38
    • /
    • 2010
  • In this paper, we suggest DCU(Digital Control Unit) for performance improvement and stability security of base station power amplifier. The designed DCU controls electric power that is supplied to power amplifier. When the regular input is 10dBm, the regular output is measured 47.8dBm and the results are compared between the case of the applying and the non-applying the DCU. We got the result that PA system is very stable as DCU are very well operating in the boundary degradation of IMD by the over-power level input.

Design of the Low Noise Amplifier and Mixer Using Newly Bias Circuit for S-band (새로운 바이어스 회로를 적용한 S-band용 저잡음 증폭기 및 믹서의 One-Chip 설계)

  • Kim Yang-Joo;Shin Sang-Moon;Choi Jae-Ha
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.16 no.11 s.102
    • /
    • pp.1114-1122
    • /
    • 2005
  • In this paper, the study of a design, fabrication and measurement of the receiver MMIC LNA, mixer for S-band application is described. The LNA is designed by 2-stage common source. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The LNA has 15.51 dB-gain and 1.02dB-Noise Figure at 2.1 GHz. The conversion gain of the mixer is -12 dB, IIP3 is approximately 4.25 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.2[mm]\times1.4[mm]$.