• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.12
• /
• pp.1-9
• /
• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.2
• /
• pp.189-194
• /
• 2018

Nowadays most integrated circuits are built using the bulk CMOS technology, but it has much difficulty in further reduction of the power consumption and die size. As a super low-power technology to solve such problems, the SOI technology attracts great attention recently. In this paper, the study results of the temperature dependency of the hot carrier effects in the n-channel MOSFETs fabricated on the thin SOI substrate were discussed. In spite that the devices employed the LDD structure, the hot carrier effects were more serious than expected due to the high series resistance between the channel region and the substrate contact to the ground, and were found to be less serious for the higher temperature with the more phonon scattering in the channel region, which resulted in reducing the hot electron generation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.9
• /
• pp.1615-1622
• /
• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.6
• /
• pp.390-397
• /
• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.317-320
• /
• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.1
• /
• pp.103-108
• /
• 2002

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade In response to the constant demand for increased speed, decreased power, and increased packing density. The state -of-the-art simulation programs are developed by engineers and scientists. This paper has compared commercial programs of Micro-tec and ISE-TCAD in device simulation. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths(Lg) 180㎚. We have presented MOSFET's characteristics such as I-V characteristic and electric field, and compared Micro-tec with ISE TCAD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.749-752
• /
• 2014

The device performance of n-channel MuGFET with different fin width, existence of spacer and channel length has been characterized. Tri-Gate structure(fin number=10) has been used. There are four kinds of Tri-Gate with fin width=55nm with spacer, fin width=70nm with spacer, fin width=55nm without spacer, fin width=70nm without spacer. DIBL, subthreshold swing, Vt roll-off, (above Short Channel Effect)and hot carrier stress degradation have been measured. From the experiment results, short Channel Effect with spacer was decreased, hot carrier degradation with spacer and narrow fin width was decreased. Therefore, layout of LDD structure with spacer and narrow fin width is desirable in short channel effect and hot carrier degradation.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1258-1261
• /
• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.8
• /
• pp.49-56
• /
• 1993

In this paper, we present a new lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and substrate current influence. The suggested model is applied to a different channel structured PMOSFET, dgm/gm of both SC-PMOSFET and BC-PMOSFET appear with one straigth line about Qbib, therefore, this model is independent of channel structure. The suggested model is applied to a different drain structured SC-PMOSFET. Unlike S/D structured SC-PMOSFET, dgm/gm of LDD structured SC-PMOSFET appears with one straight line about Qb, therefore, this model is dependent of drain structure.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.1
• /
• pp.61-64
• /
• 1994

The NMOSFET with gate length of 0.1$\mu$m is fabricated by mix-and-match method. In this device, the electron beam lithography is used to form the gate layer, while other layers are formed by the stepper. The gate oxide is 7nm thick, and the device structure is normal LDD structure. The saturation Gm for gate length of 0.1$\mu$m is 246mS/mm. The subthreshold slope is 180mV/decade for 0.1$\mu$m gate length, but the slope is 80mV/decade for 0.3$\mu$m gate length.