• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.33-39
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• 2006

In this paper we propose the Modified Karatsuba-Ofman algorithm for polynomial multiplication to polynomials of arbitrary degree. Leone proposed optimal stop condition for iteration of Karatsuba-Ofman algorithm(KO). In this paper, we propose a Non-Redundant Karatsuba-Ofman algorithm (NRKOA) with removing redundancy operations, and design a parallel hardware architecture based on the proposed algorithm. Comparing with existing related Karatsuba architectures with the same time complexity, the proposed architecture reduces the area complexity. Furthermore, the space complexity of the proposed multiplier is reduced by 43% in the best case.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.33-40
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• 2004

The divide-and-conquer method is efficiently used in parallel multiplier over finite field $GF(2^n)$. Leone Proposed optimal stop condition for iteration of Karatsuba-Ofman algerian(KOA). Ernst et al. suggested Multi-Segment Karatsuba(MSK) method. In this paper, we analyze the complexity of a parallel MSK multiplier based on the method. We propose a new parallel MSK multiplier whose space complexity is same to each other. Additionally, we propose optimal stop condition for iteration of the new MSK method. In some finite fields, our proposed multiplier is more efficient than the KOA.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.129-131
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• 2004

Elliptic Curve Cryptography (ECC) coprocessors support massive scalar multiplications of a point. We research the design for multi-segment multipliers in fixed-size ECC coprocessors using the multi-segment Karatsuba algorithm on GF($2^m$). ECC coprocessors of the proposed multiplier is verified on the SoC-design verification kit which embeds ALTERA EXCALIBUR FPGAs. As a result of our experiment, the multi-segment Karatsuba multiplier, which has more efficient performance about twice times than the traditional multi-segment multiplier, can be implemented as adding few H/W resources. Therefore the multi-segment Karatsuba multiplier which satisfies performance for the cryptographic algorithm, is adequate for a low cost embedded system, and is implemented in the minimum area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.1-9
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• 2007

For an efficient implementation of cryptosystems based on arithmetic in a finite field $GF(2^n)$, their hardware implementation is an important research topic. To construct a multiplier with low area complexity, the divide-and-conquer technique such as the original Karatsuba-Ofman method and multi-segment Karatsuba methods is a useful method. Leone proposed an efficient parallel multiplier with low area complexity, and Ernst at al. proposed a multiplier of a multi-segment Karatsuba method. In [1], the authors proposed new $MSK_5$ and $MSK_7$ methods with low area complexity to improve Ernst's method. In [3], the authors proposed a method which combines $MSK_2$ and $MSK_3$. In this paper we propose an efficient multiplication method by combining $MSK_2,\;MSK_3\;and\;MSK_5$ together. The proposed method reduces $116{\cdot}3^l$ gates and $2T_X$ time delay compared with Gather's method at the degree $25{\cdot}2^l-2^l with l>0.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.121-126
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• 2014

The problem of finding the fastest algorithm for multiplication of two large n-digit decimal numbers remains unsolved in the field of mathematics and computer science. To this problem so far two algorithms - Karatsuba and Toom-kook - have been proposed to shorten the number of multiplication. In the complete opposite of shorten the number of multiplication method, this paper therefore proposes an efficient multiplication algorithm using additions completely. The proposed algorithm totally applies shift-and-add algorithm of binary system to large digits of decimal number multiplication for example of RSA-100 this problem can't perform using computer. This algorithm performs multiplication purely with additions of complexity of $O(n^2)$.

• ETRI Journal
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• v.41 no.6
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.4
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• pp.878-894
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• 2013

Secure multimedia multicast applications involve group communications where group membership requires secured dynamic key generation and updating operations. Such operations usually consume high computation time and therefore designing a key distribution protocol with reduced computation time is necessary for multicast applications. In this paper, we propose a new key distribution protocol that focuses on two aspects. The first one aims at the reduction of computation complexity by performing lesser numbers of multiplication operations using a ternary-tree approach during key updating. Moreover, it aims to optimize the number of multiplication operations by using the existing Karatsuba divide and conquer approach for fast multiplication. The second aspect aims at reducing the amount of information communicated to the group members during the update operations in the key content. The proposed algorithm has been evaluated based on computation and communication complexity and a comparative performance analysis of various key distribution protocols is provided. Moreover, it has been observed that the proposed algorithm reduces the computation and communication time significantly.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.3
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• pp.515-518
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• 2019

The performance of Elliptic Curves Cryptosystem(ECC) is dominated by the modular multiplication since the elliptic curve scalar multiplication consists of the modular multiplication in projective coordinates. In this paper, we propose a new method that combines the Karatsuba-Ofman multiplication method and a new modular reduction algorithm in order to improve the performance of the modular multiplication for NIST p224 in the FIPS 186-4 standard. The proposed method leads to a running time improvement for computing the modular multiplication about 25% faster than the previous methods. The results also show that the method can reduce the arithmetic complexity by half when compared with traditional implementations on the standpoint of the modular reduction.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.5
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• pp.841-853
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• 2024

This paper proposes an optimization method for the GF(2)[x] multiplication operation in HQC on AVX2. HQC is a candidate in NIST PQC standardization round 4 and is a binary code-based key exchange algorithm. The multiplication operation is one of the most time-complex operations in HQC, accounting for about 30% of the total clock cycles in the AVX2 environment. For the optimization, we used Karatsuba and Toom-Cook algorithms. Both algorithms are based on divide-and-conquer methods, which require multiplications of smaller order within them. We propose a method to optimize polynomial multiplication in HQC by finding the most efficient combination of Karatsuba and Toom-Cook algorithms, and compare the performance of the proposed method based on the implementation submitted to the PQC standardization. The results of the comparison demonstrate a performance improvement of 4.5%, 2.5%, and 30.3% over the GF(2)[x] multiplications of original hqc-128, -192, and -256. When applied to key generation, encapsulation, and decapsulation, the performance improvement over the original HQC is 2.2%, 2.4%, and 2.3% for hqc-128, 1.6%, 4.2%, and 2.6% for hqc-192, and 13.3%, 14.7%, and 13.3% for hqc-256, respectively.