• Safety and Health at Work
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• 제10권3호
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• pp.347-354
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• 2019

Background: The aim of this study was to describe the types of diseases that developed in semiconductor workers who have registered with the Korea Workers' Compensation and Welfare Service (KWCWS) and to identify potential common occupational characteristics by the type of claimed disease. Methods: A total of 55 semiconductor workers with cancer or rare diseases who claimed to the KWCWS were compared based on their work characteristics and types of claimed diseases. Leukemia, non-Hodgkin lymphoma, and aplastic anemia were grouped into lymphohematopoietic (LHP) disorder. Results: Leukemia (n = 14) and breast cancer (n = 10) were the most common complaints, followed by brain cancer (n = 6), aplastic anemia (n = 6), and non-Hodgkin lymphoma (n = 4). LHP disorders (n = 24) accounted for 43%. Sixty percent (n = 33) of registered workers (n = 55) were found to have been employed before 2000. Seventy-six percent (n = 42) of registered workers and 79% (n = 19) among the registered workers with LHP (n = 24) were found to be diagnosed at a relatively young age, ${\leq}40years$. A total of 18 workers among the registered semiconductor workers were finally determined to deserve compensation for occupational disease by either the KWCWS (n = 10) or the administrative court (n = 8). Eleven fabrication workers who were compensated responded as having handled wafers smaller than eight inches in size. Eight among the 18 workers compensated (44 %) were found to have ever worked at etching operations. Conclusion: The distribution of cancer and rare diseases among registered semiconductor workers was closely related to the manufacturing era before 2005, ${\leq}8$ inches of wafer size handled, exposure to clean rooms of fabrication and chip assembly operations, and etching operations.

• Transactions on Electrical and Electronic Materials
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• 제14권6호
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1269-1271
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• 2008

We find some array mura are caused by S/D bridge or channel open in 4 mask process. The gray tone PR thickness non-uniformity is the main reason of these defects. By the adjustment of exposure and dry etch parameters, S/D bridge and channel open ratio drops by 10.87%.

• 전자공학회논문지A
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• 제32A권3호
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• 한국정밀공학회지
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• 제23권7호
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• 한국세라믹학회지
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• 제43권4호
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• pp.220-223
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• 2006

BLT nanotubes were synthesized by using simple and convenient method template-wetting process. Porous alumina membranes were prepared by 2 step anodic oxidation as the template. To improve wetting properties and make low surface energy, BLT solution was mixed with polymer. Polymer was removed completely during annealing. After completely etching the template in 30 wt% KOH solution, we demonstrate that BLT nanotubes with a diameter of 200 nm can be fabricated. Grain growth process of BLT nanotubes during baking, and furnace annealing was examined by FE-SEM and XRD.

• Bulletin of the Korean Chemical Society
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• 제30권7호
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• pp.1593-1597
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• 2009

A biosensor has been developed based on induced wavelength shifts in the Fabry-Perot fringes in the visible reflection spectrum of appropriately derivatized thin films of porous silicon semiconductors. Porous silicon (PSi) was generated by an electrochemical etching of silicon wafer using two electrode configurations in aqueous ethanolic HF solution. Porous silicon displayed Fabry-Perot fringe patterns whose reflection maxima varied spatially across the porous silicon. The sensor system studied consisted of a mono layer of porous silicon modified with Protein A. The system was probed with various fragments of an aqueous Human Immunoglobin G (Ig G) analyte. The sensor operated by measurement of the Fabry-Perot fringes in the white light reflection spectrum from the porous silicon layer. Molecular binding was detected as a shift in wavelength of these fringes.

• ETRI Journal
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• 제27권4호
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• pp.433-438
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• 2005

We present a new type of silicon micro-probe card using a three-dimensional probe beam of the cantilever type. It was fabricated using KOH and dry etching, a porous silicon micromachining technique, and an Au electroplating process. The cantilever-type probe beam had a thickness of $5 {\mu}m$, and a width of $50{\mu}$ and a length of $800 {\mu}m$. The probe beam for pad contact was formed by the thermal expansion coefficient difference between the films. The maximum height of the curled probe beam was $170 {\mu}m$, and an annealing process was performed for 20 min at $500^{\circ}C$. The contact resistance of the newly fabricated probe card was less than $2{\Omega}$, and its lifetime was more than 20,000 turns.

• 통합자연과학논문집
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• 제4권1호
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• pp.11-14
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• 2011

Free-standing multilayer distributed Bragg reflectors (DBR) porous silicon dielectric mirrors, prepared by electrochemical etching of crystalline silicon using square wave currents are treated with polymethylmethacrylate (PMMA) to produce flexible, stable composite materials in which the porous silicon matrix is covered with caffeine-impregnated PMMA. Optically encoded free-standing DBR PSi dielectric mirrors retain the optical reflectivity. Optical characteristics of free-standing DBR PSi dielectric mirrors are stable and robust for 24 hrs in a pH 12 aqueous buffer solution. The appearance of caffeine and change of DBR peak were simultaneously measured by UV-vis spectrometer and Ocean optics 2000 spectrometer, respectively.