• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.4
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• pp.93-99
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• 2011

This paper proposes a novel network jitter estimation algorithm for robust VoIP communication system. The proposed method computes the current network environment mode using the differences of arrival time and generation time from sequential received packets. According to the current network environment mode, the jitter variance weights is adjusted to minimize the error for estimating the network jitter. The jitter average and variance are calculated by the autoregressive estimated algorithm, and then the network jitter is estimated by applying the jitter variance weights.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.429-438
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• 2004

In this paper, a decision-feedback coherent code tracking loop is designed for WCDMA systems and its performance is analyzed in terms of jitter variance considering the effect of phase and symbol estimation errors for both AWGN and fading environments. An analytical closed-form formula for jitter variance is Int derived for AWGN environments as a function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth while involving the phase estimation error and bit error rate, and the upper bound of jitter variance is derived for fading environments. Finally a second-order coherent code tracking loop is designed with the DPCH frame format #13 of the WCDHA forward link selected as a target system, and its performance is evaluated by the closed-form formula and compared with the simulation results for both AWGN and Rayleigh fading environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.983-990
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• 2003

In this paper, a noncoherent code tracking loop is designed for 3GPP MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. An analytical closed-form formula for steady-state jitter variance is Int derived for AWGN environments as a general function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth, together with the analysis on the transient response characteristic of a tracking loop. Based on the analysis, the code tracking loop with variable loop bandwidth that is efficient for full digital H/W implementation is designed and its performance is compared with that of the code tracking loop with fixed loop bandwidth, along with the verification by computer simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of Advanced Navigation Technology
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• v.7 no.1
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• pp.6-13
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• 2003

In this paper, a non-coherent code tracking loop is designed for 3GPP HSDPA MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. Analytical closed-form formula for steady-state jitter variance is first derived for AWGN environments as a function of pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. Also obtained is the transient response characteristic of a tracking loop. Finally, the performance of the designed tracking loop is confirmed by computer simulations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.1-9
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• 1996

in this paper, we analyzed CDD-DLL code tracking loop for tracking of direct-sequence spread-spectrum signals in a multipath fading channel. The multipath fading channel is modeled as two-ray rayleigh fading channel which is well applicable in a land mobile communication environments. We use trackin jitter variance and mean-time-to-lose-lick as performance measures. From the numerical resutls, it is shown that the effect of multipath fading decreases as SNR/bit increases. Also it is shown that CDD-DLL provides superior jitter performance compared with noncoherent DLL and jitter performance improvement is more significant for a two-ray rayleigh fading channel than an AWGN channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.386-392
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• 2002

Internet telephony is an application that transmits voice data for conversation. Therefore it must provide high sound quality. However while audio packets are transferred through the network, they are affected by delay variations and jitters, which could result in poor sound quality of the receiving end does not have an appropriate jitter buffer to overcome network factors. This thesis introduces a buffer management algorithm that could be used to provide better sound quality for Internet phone terminals. This algorithm actively responds to both the compression algorithms that are used by the terminals, as well as to the received data to provide an improvement in sound quality. In order to verify the effectiveness of the proposed algorithm, we experimented in variance network settings. The results show that the proposed algorithm improves on the performance of the conventional buffer management algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10B
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• pp.916-926
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• 2003

The encryption of packets increases delay and delay jitter that may degrade the quality of service (QoS) in real-time communications. So, we analyzed the delay jitter, delay, and interval delay between consecutive packets which were encrypted by the DES, 3DES, SEED and AES algorithms in this study. The interval delay and jitter of three algorithms such as the DES, SEED, AES were similar to the results of no encryption. But in the case of 3DES, the encryption of packets increases the variance of interval delay and jitter in comparison with other algorithms. we also analyzed properties of security and an efficiency of RTP security between SRTP and H.235.