• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.199-207
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• 2001

We propose an adaptive shaping controller equipped with the technologies of shaping and buffering VoIP packets arriving at the receiving end by the CAM-type controller. In order to conceal interarrival packet delay variation, the conventional jitter buffers force them to be too large, thereby causing the audio quality to suffer excessive delay. However, by using our proposed method, the delay caused by shaping operation dynamically increases or decreases on the level of jitter that exists with in the IP network. This makes the delay accommodates adaptively the network jitter condition. The less jitter network has the fewer delay the shaping controller requires for jitter elimination. And the CAM-type method generally makes the shaping operation faster and leads to processing packets in as little time as can. We analyse the packet loss and delay performance dependency on the average talk ratio and the number of jitter buffer entries in shaping controller. Surprising, we show that the average delay using our shaping controller is about 70msec. This performance is much better than with the delay equalization method which forces the receiving end to delay about 60msec.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.153-158
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• 1996

Delay and jitter are critical factors in the real-time video services over ATM network. Mostly, delay and jitter problem are generated in input buffer when video are multiplexed. In this paper, we analyze delay and jitter of input buffer, and consider efficient control and flexible bandwidth allocation of video traffic. Also, we analyze decision of buffer size related maximum allowable delay.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.4
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• pp.1006-1025
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• 2012

Improving the quality of service in IP networks is a major challenge for real-time voice communications. In particular, packet arrival-delay variation, so-called "jitter," is one of the main factors that degrade the quality of voice in mobile devices with the voice-over Internet protocol (VoIP). To resolve this issue, a receiver-based enhanced timing recovery algorithm combined with active jitter estimation is proposed. The proposed algorithm copes with the effect of transmission jitter by expanding or compressing each packet according to the predicted network delay and variations. Additionally, the active network jitter estimation incorporates rapid detection of delay spikes and reacts to changes in network conditions. Extensive simulations have shown that the proposed algorithm delivers high voice quality by pursuing an optimal trade-off between average buffering delay and packet loss rate.

• Journal of the Optical Society of Korea
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• v.13 no.3
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• pp.373-378
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• 2009

An Ethernet passive optical network (EPON) is a low-cost, high-speed solution to the bottleneck problem of a broadband access network. This paper analyzes the delay and the jitter performance of dynamic bandwidth allocation (DBA) schemes for differentiated services in EPONs. Especially, the average packet delay and the delay jitter of the expedited forwarding (EF) traffic class are compared, with consideration as to whether a cyclic or an interleaved polling scheme is superior. This performance evaluation reveals that the cyclic polling based DBA scheme provides constant and predictable average packet delay and improved jitter performance for the EF traffic class without the influence of load variations.

• 전자공학회논문지 IE
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• v.48 no.3
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• pp.1-9
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• 2011

In this paper, we develop an analytical expression for the propagation delay of submicrometer CMOS inverter using the triangle-shaped waveform of output current and two fitting parameters. Our model shows that simulation results are well in accordance with HSPICE results. Maximum simulation errors of total inverter delay and jitter are below 0.6% and 2.8%, respectively. Comparing with previous researches, the new model has better fittering characteristics in the range of low operating voltage. We also have fabricated the inverters with ten chains and estimated inverter delay and jitter characteristics. The results show that the values of delay and jitter in the fabricated samples come close to the values of those in the new model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Journal of IKEEE
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• v.25 no.2
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• pp.234-242
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• 2021

In case implementation of microwave photonic (MWP) systems for phased array radars (PARs), noise and time delay error should be minimized to obtain accurate beam direction. Time delay error in MWP systems is generated from signal noise and timing jitter. In this paper, noise and timing jitter in MWP systems for PAR is researched, also according to the amplification of an erbium-doped fiber amplifier, noise and timing jitter variation is verified by an experiment. Timing jitter is decreased and SNR is increased if we amplify the signal by using an erbium-doped fiber amplifier, up to the amplification rate of signal and noise is similar.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10B
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• pp.916-926
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• 2003

The encryption of packets increases delay and delay jitter that may degrade the quality of service (QoS) in real-time communications. So, we analyzed the delay jitter, delay, and interval delay between consecutive packets which were encrypted by the DES, 3DES, SEED and AES algorithms in this study. The interval delay and jitter of three algorithms such as the DES, SEED, AES were similar to the results of no encryption. But in the case of 3DES, the encryption of packets increases the variance of interval delay and jitter in comparison with other algorithms. we also analyzed properties of security and an efficiency of RTP security between SRTP and H.235.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.