• 한국전산유체공학회:학술대회논문집
• /
• 2011.05a
• /
• pp.117-123
• /
• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2008.05a
• /
• pp.216-219
• /
• 2008

The Power LED is more much than 1W and appliable to lights that is different from signal LED. In this paper we investigated types of tests in reliability assessment standards on Power LED. we make comparison of that military standards, JEITA(Japan Electronics and Information Technology Industries Association) and JEDEC(Joint Electron Device Engineering Council) with RS(reliability standard). Reliability tests should be considered that informations can be obtained from requirements of a real system Therefore, The paper aided companies to criteria for reliability tests by themselves.

• Proceedings of the KSME Conference
• /
• 2008.11a
• /
• pp.1289-1294
• /
• 2008

Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.

• Journal of Advanced Navigation Technology
• /
• v.24 no.4
• /
• pp.314-321
• /
• 2020

Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.