• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.114-118
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• 2016

In this paper, we present the advanced open collector circuit, interface circuit between aerospace electronics. Satellite is composed of a number of electronics, which were provided from various manufacturers. Each company manufactured its own electronics for satellite using its heritage and requirements for their electronics. Therefore each electronics may use different internal supplies. It make a problem between electronics because the supply is different from other electronics, such as the increasing of power dissipation because of the static current and the mismatch of interface voltage, the offset. Proposed circuit can reduce the static current and rising time, and also decrease the useless power dissipation caused by the static current for open collector circuit

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.5-5
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• 2001

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.274-275
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• 2007

The investigation of the equivalent circuit models for the electrode/electrolyte interface has been pursued for a long time by several researchers. Previous circuit models fit the experimental results in limited conditions such as frequency range, type of electrode, or electrolyte. This paper describes a new electrical circuit model and its capability of fitting the experimental results. Electrochemical impedance spectroscopy was used to characterize the interface for Au, Pt, and stainless steel electrode in 0.9% NaCl solution. Both the proposed model and the previous model were applied to fit the measured impedance results for comparison. The proposed model fits the experimental data more accurately than other models especially at the low frequency range, and it enables us to predict the impedance at very low frequency range, including DC, using the proposed model.

• Progress in Superconductivity
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• v.3 no.1
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• pp.87-90
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• 2001

We designed a high temperature superconducting rapid single flux quantum(RSFQ) T flip-flop(TFF) circuit using Xic and WRspice. According to the optimized circuit parameters, we fabricated the TFF circuit with $Y_1$$Ba_2$Cu$_3$$O_{7-x}$(YBCO) interface-controlled Josephson junctions. The whole circuit was comprised of five epitaxial layers including YBCO ground plane. The interface-controlled Josephson junction was fabricated with natural junction barrier that was formed by interface-treatment process. In addition, we report second design for a new flip-flop without ground palne.e.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1998.04a
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• pp.444-449
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• 1998

A modal transducer in two-dimensional structure can be implemented by varying the distributed transducer's gain spatially. In this paper, a method based on finite element method is developed for optimizing spatial gain distribution of PVDF transducer to create the modal transducer for specific modes. Using this concept, one can design the modal transducer in two-dimensional structure having arbitrary geometry and boundary conditions. As a practical means for implementing this continuous gain distribution without repoling die PVDF film, the gain distribution is approximated by optimizing gain-weights of interface circuit. The whole spatial area of the PVDF film is divided into several electrode segments and the signals from each segment are properly weighted and summed by interface circuit. This corresponds to the approximation of a continuous function using discrete values. The electrode partition is optimized using the genetic algorithm. Gain-weights are optimized using the simplex search method. A modal sensor for first to fourth modes of aluminum plate is designed using PVDF film with gain-weighted interface circuit. Various lamination angles of PVDF film are taken into consideration to utilize the anisotropy of the PVDF film. Performance of the optimized' PVDF sensor is demonstrated by numerical simulations..

• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• Journal of IKEEE
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• v.27 no.1
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• pp.45-52
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• 2023

Cold-junction correction(CJC) and disconnection detection circuit design of various thermocouples(TC) and multi-channel TC interface circuit using them were designed. The CJC and disconnection detection circuit consists of a CJC semiconductor device, an instrumentation amplifier(IA), two resistors and a diode for disconnection detection. Based on the basic circuit, a multi-channel interface circuit was also implemented. The CJC was implemented using compensation semiconductor and IA, and disconnection detection was detected by using two resistor and a diode so that IA input voltage became -0.42V. As a result of the experiment using R-type TC, the error of the designed circuit was reduced from 0.14mV to 3㎶ after CJC in the temperature range of 0℃ to 1400℃. In addition, it was confirmed that the output voltage of IA was saturated from 88mV to -14.2V when TC was disconnected from normal. The output voltage of the designed circuit was 0V to 10V in the temperature range of 0℃ to 1400℃. The results of the 4-channel interface experiment using R-type TC were almost identical to the CJC and disconnection detection results for each channel. The implemented multi-channel interface has a feature that can be applied equally to E, J, K, T, R, and S-type TCs by changing the terminals of CJC semiconductor devices and adjusting the IA gain.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.1
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• pp.67-75
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• 2002

This paper presents a PLD design of Gray Mode Graphic STN LCD drive circuit using PC interface. The proposed LCD drive circuit doesn\`t use microprocessor for the convenience of users. Thus, the LCD drive circuit can transfer efficiently image data created under PC to LCD. The LCD drive circuit which is modelled in schematic capture, AHDL and VHDL is simulated in functionally through the use of ALTERA MAX+PLUS II. Also, timing simulation is performed by ALTERA EPM7192SQC160-15 PLD implementation. The PC interface part have been programmed in MS-Visual C++ 6.0. The validity and efficiency of the proposed LCD drive circuit have been verified by test board. After comparing this LCD drive circuit to specify it was verified that the developed LCD drive circuit showed good performances, such as convenience of users, low cost.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.167-168
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• 2000

We propose a signaling circuit that can reduce power consumption and Electromagnetic Interference (EMI) in a Liquid Crystal Display (LCD) controller-to-source driver interface. The proposed signaling circuit consists of a coder/decoder that can minimize temporal bit transitions in a transmission line and a current-mode driver that can convert voltage swing into a very small amount of current. We have simulated the proposed signaling circuit using the HSPICE and the proposed signaling circuit has been designed in a 0.25 ${\mu}m$ CMOS technology.