• Journal of Korea Multimedia Society
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• v.24 no.7
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• pp.913-921
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• 2021

After arranging the general usability evaluation criteria of existing VUI researchers, this study verified how appropriate these criteria are for AI VUI specialized in navigation and the priority of their suitability. The VUI used in this study was analyzed through a survey from a total of 195 Chinese users after analyzing the navigation VUI used in China. As a result of the analysis, the usability evaluation criteria of the navigation VUI were extracted from three sub-factors of 'task accuracy', 'function satisfaction', and 'information reliability' in verifying conformance with general VUI evaluation criteria. With the recent advent of self-driving cars, safety and response speed are becoming very important, so Chinese users also ranked responsiveness as the top priority in VUI design, and the importance was also found to be high. Also, both men and women have the highest reactivity and the lowest multiplicity. VUI requires a convenient and natural interface to understand the intention between two objects through usability evaluation and verification in order to have effective interaction between humans and machines.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1781-1785
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• 2007

We propose a new enhanced graphical user interface and algorithm for dynamic signature verification using Smart-phone. Also, we describe the performance results of our dynamic signature verification system, which determine the authentication of signatures by comparing and analyzing various dynamic data shape of the signature, writing speed, slant of shape, and the order and number of strokes for personal signatures using an electronic pen, expecting the system to be understood and utilized widely in the industrial field.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.544-547
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• 2007

Because data processing systems in recent years are more complicated, main function of the data processing is divided as several sub-functions which are implemented and verified in each subsystem of the data processing system. For the verification of data processing system, many interface tests among subsystems are required and also a lot of simulation systems are demanded. This paper proposes CTHS (Common Test Harness System) for satellite ground segment development which has all of functions for interface test of the data processing system in one PC. Main functions of the CTHS software are data interface, system log generation, and system information display. For the interface test of the data processing system, all of actions of the CTHS are executed by a pre-defined operation scenario which is written by purpose of the data processing system test.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.93-96
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• 2002

It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Smart Media Journal
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• v.9 no.4
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• pp.73-80
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• 2020

With the advent of the Internet era, consumer lifestyles have been changed tremendously, and mobile payment has carried out an increasingly extensive coverage of the people's life trajectory. Taking the design of the mobile payment interface as an example, we use a conjoint analysis method to survey college students in Guangxi, where questionnaires are collected from 270 people in different groups according to gender. The method separates the attributes that affect consumer choice of mobile payment interface design and the utility value of the attribute level to analyze consumer needs and preferences, and then obtains consumers' potential evaluation criteria for mobile payment interface design. The results of the study show that the attributes that influence consumers' choice of mobile payment interface design are, in order of preference: page layout, identification convenience, verification, module distribution, entertainment, and information encryption. Consumer groups of different genders show differences in their preferences in the mobile payment interface design and Consumer needs reflect consumer psychology. Several findings are obtained on the consumers' preferences on the mobile payment interface design, which may be used to improve future design processes.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.427-428
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• 2008

본 논문에서는 IEEE 802.11 MAC Layer의 Reception, Transmission 검증을 위해 PLI (Programing Language Interface)를 이용한 방법을 제안한다. PLI를 이용한 검증은 시스템 Level의 검증으로써 설계단계에서 문제점을 확인하고 수정할 수 있다. 그러므로 불필요한 개발비의 낭비를 줄일 수 있고 개발 기간 단축의 효과를 거둘 수 있다. 검증을 위해 Mentor Graphics 사의 HDL (Hardware Description Language) 시뮬레이터인 Modelsim 6.1g Version을 사용하고 PLI를 이용하여 검증 환경을 구축한다.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.183-186
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• 2007

The aim of this analysis is to verify the electrical compatibility of the interfaces which exist between COMS(Communication, Ocean and Meteorological Satellite) AOCS(Attitude Orbit Control Subsystem) equipments and external equipments. For each interface, this study checked the compatibility between equipments for the power links, commands, digital telemetry, analog telemetry and failure condition. In addition with this interface compatibility verification, this study outputs the electrical and manufacturing constraints to be applied at harness level.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.