High-Level Design Verification Techniques for Hardware-Software Codesign Systems

하드웨어-소프트웨어 통합 설계 시스템을 위한 상위 단계에서의 검증 기법

  • 이종석 (현대전자 메모리연구소 응용제품팀) ;
  • 김충희 (한양대학교 전자공학과) ;
  • 신현철 (한양대학교 전자공학과)
  • Published : 2000.08.31

Abstract

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

설계되는 시스템의 규모가 커지고 복잡해지므로 이를 빠른 시간 내에 효율적으로 검증하기 위한 상위 단계에서의 검증 기술의 개발이 중요하게 되었다. 본 연구에서는 하드웨어와 소프트웨어가 혼합되어 있는 시스템을 위한 상위 단계에서의 검증기술을 개발하였다. 에뮬레이션 또는 시뮬레이션만을 수행하는 것보다 빠르고 우수하게 기능적으로 검증하기 위해, 하드웨어와 소프트웨어 부분으로 분할한 후 인터페이스 회로를 이용하여 구현 가능하도록 하였다. 그리고, 상위 단계의 회로를 쉽게 하드웨어를 이용하여 검증하기 위한 설계 지침들을 제시하였다. 본 방법을 이용하여 리드-솔로몬 디코더 회로에 대한 검증을 수행한 결과 시뮬레이션만을 수행한 경우에 비하여 modified Euclid 알고리즘 수행 블록은 12,000배 이상의 속도로 검증을 수행할 수 있었으며, 전체 검증 시간도 반 이하로 줄었다.

Keywords

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