• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.11
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• pp.3955-3966
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• 2014

With the exponentially increasing Internet traffic and emergence of more versatile and heterogeneous applications, the design of datacenter networks (DCNs) is subject to unprecedented requirements for larger capacity and more flexible switching granularities. Envisioning Optical-Orthogonal Frequency Division Multiplexing (O-OFDM) as a promising candidate for such a scenario, we motivate the use of O-OFDM as the underlying switching technology in order to provide sufficient switching capacity and elastic bandwidth allocation. For this purpose, this article reviews the recent progresses of DCN deployment and assesses the scenario where the O-OFDM transmission and switching technology is employed in the underlying transport plane. We discuss the key issues of the datacenter-oriented O-OFDM optical networks, and in particular, elaborate on a number of open issues and solutions including system interconnection architecture, routing and resource assignment, survivability, and energy-efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.7
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• pp.3275-3279
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• 2011

The matter of the calculation of the mutual access fee has become one of the hottest issues among service providers and attracted concerns from concerned regulatory authorities. It is essential to conclude a rational and systematic procedure for interconnection costs and charge between fixed and mobile networks. In this paper, I proposed the conversion factor scheme between circuit switched voice and packet switched data service in the domestic CDMA mobile system based on analysis of the rational GSM allocation method of common cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1116-1121
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• 2014

Mesh structure is one of typical interconnection networks, and it is used in the part of VLSI circuit design. Torus and Hyper-Torus are advanced interconnection networks in the part of diameter and fault-tolerance of mesh structure. In this paper, we will analyze embedding between Torus and Hyper-Torus networks. We will show T(4k,2l) can be embedded into QT(m,n) with dilation 5, congestion 4, expansion 1. And QT(m,n) can be embedded into T(4k,2l) with dilation 3, congestion 3, expansion 1.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.10
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• pp.789-796
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• 2006

An unpaired many-to-many k-disjoint nth cover (k-DPC) of a graph G is a set of k disjoint paths joining k distinct sources and sinks in which each vertex of G is covered by a path. Here, a source can be freely matched to a sink. In this paper, we investigate unpaired many-to-many DPC's in a subclass of hpercube-like interconnection networks, called restricted HL-graphs, and show that every n-dimensional restricted HL-graph, $(m{\geq}3)$, with f or less faulty elements (vertices and/or edges) has an unpaired many-to-many k-DPC for any $f{\geq}0\;and\;k{\geq}1\;with\;f+k{\leq}m-2$.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.35-43
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• 2004

In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. However, Ding and Bhuyan has shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an analytical model for evaluating the performance of input-buffered MlN's employing this network cycle approach is proposed, The effectiveness of the proposed model is confirmed by comparing results from the simulation as well as from Ding and Bhuyan model.

• Journal of Internet Computing and Services
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• v.5 no.1
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• pp.41-49
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• 2004

Analytical performance evaluation is crucial for justifying the merit of the design of Multistage Interconnection Networks(MINs) in different operational conditions. While several analytical models have been proposed for the performance evaluation of MlNs, they are mainly for uniform traffics. Even the models for nonuniform traffics have various shortcomings. In this paper, an accurate model for the performance evaluation of multi buffered banyan-type MIN's under nonuniform traffic condition is obtained. The accuracy of proposed models are conformed by comparing with the results from simulation.

• Journal of Internet Computing and Services
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• v.4 no.5
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• pp.43-49
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• 2003

Analytical performance evaluation is crucial for justifying the merit of the design in different operational conditions. While several analytical models have been proposed for the performance evaluation of Multistage Interconnection Networks(MINs), they are mainly for uniform traffics. Even models for nonuniform traffics have several shortcomings such as they only consider output buffered structure or do not consider blocking conditions. In this paper the mere accurate models than any other ones so far have been proposed for the performance evaluation of banyan-type MIN's under nonuniform traffic condition is obtained. The accuracy of proposed model is conformed by comparing with the results from simulation.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.375-378
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• 2001

A 640Gb/s very advanced ATM switching system using 0.25um CMOS VLSI, 40 layer ceramic MCM and 10Gb/s, 8 wavelength 8$\times$8 optical WDM interconnection has been fabricated. To break though the interconnection bottleneck, optical WDM interconnection is used. It has 20Gb/s 8 wavelength 8$\times$8 interconnection capability. It realizes 640Gb/s interconnections within a very small size. Preliminary tests show that 800b1s ATM switch MCM and optical WDM interconnection technologies can be applied to future high speed broadband networks

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1490-1495
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• 1998

Call packing has been recognized as a routing scheme that significantly reduces the blocking probability of connection requests in a circuit-switched Clos multistage interconnection network. In this paper, for the first time, a general analytical model for the point-to-point blocking probability of the call-packing scheme applied to Clos networks is developed. By introducing a new parameter called the degree of call packing, the model can correctly estimate the blocking probability of both call-packing and random routing schemes. The model is verified by computer simulation for various size networks and traffic conditions.