• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.53-59
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• 2004

This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method is based on applying numerical 2-dimensional capacitance extraction formula for 3-dimensional interconnect models. This method improves the extraction efficiency 952 times while compromising the accuracy within 1.8 percentage of maximal relative error, compared with the results of Fastcap program for various 3-D models. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.47-54
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• 2005

In this paper, novel test patterns and on-chip data are presented to indicate that the variation of coupling capacitance, ${\Delta}Cc$ by crosstalk can be larger than static coupling capacitance, Cc. It is also shown that ${\Delta}Cc$ is strongly dependent on the phase of aggressive lines. for anti-phase crosstalk ${\Delta}Cc$ is always larger than Cc while for in-phase crosstalk ${\Delta}Cc$ is smaller than Cc. HSPICE simulation shows good agreement with the measurement data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.1-8
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• 2000

In this paper, the dependence of interconnect line-induced delay time on the size of CMOSFET gate width is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as transistor size increases. However, there exists a transistor size for minimum total delay time when both of resistance and capacitance of interconnect line become larger than those of transistor. The optimum transistor size for minimum total delay time is obtained using an analytic equation and the experimental results showed good agreement with the calculation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.59-68
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• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.979-982
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• 1999

A new accurate as well as efficient multi-layer interconnect capacitance extraction method is presented. Since Multi-layer interconnects is too complicated to directly extract capacitances, it is simplified with virtual ground concept. To make the structure tractable, the shielding effects should be separately determined. Since the electric field shielding effects, and the solid-ground-based capacitance matrices can be readily determined from the layout geometry, the accurate as well as efficient quasi-3D capacitances concerned with an objective line can be readily determined. In order to demonstrate its efficiency and accuracy, the parameters and circuit responses were benchmarked with 3D-field-solver-based results.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1225-1228
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• 2003

본 논문에서는 Coupling capacitance 변화량이 Static coupling capacitance 값보다 클 수 있다는 것을 새로운 테스트 회로를 이용하여 실험적으로 증명하였다. 테스트 회로는 배선의 지연시간이 배선의 저항보다는 배선의 정전용량에만 의존하도록 하여 배선의 지연시간을 평가함으로써 배선의 정전용량의 변화 즉, Coupling capacitance 의 변화량을 정확히 평가할 수 있도록 하였다. 0.15 ㎛ CMOS 기술을 이용하여 실험한 결과 In-phase crosstalk 인 경우에는 변화량이 Static coupling capacitance 보다 작았지만 Anti-phase 인 경우에는 Static coupling capacitance 보다 크게 나타남을 보여주고 있다. 따라서 배선에 의한 정확한 지연시간 평가를 위해서는 Crosstalk 이 발생한 경우의 Coupling capacitance 변화량을 정확히 반영하는 것이 매우 필요함을 알 수 있다.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.612-614
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• 1998

As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.209-215
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• 2001

In this paper a method for analysis and modelling of coplanar transmission interconnect lines that are placed on top of silicon-silicon oxide substrates is presented. The potential function is expressed by series expansions in terms of solutions of the Laplace equation for each homogeneous region of layered structure. The expansion coefficients of different series are related to each other and to potentials applied to the conductors via boundary conditions. In the plane of conductors, boundary conditions are satisfied at $N_d$ discrete points with $N_d$ being equal to the number of terms in the series expansions. The resulting system of inhomogeneous linear equations is solved by matrix inversion. No iterations are required. A discussion of the calculated line admittance parameters as functions of width of conductors, thickness of the layers, and frequency is given. The interconnect capacitance and conductance per unit length results are given and compared with those obtained using full wave solutions, and good agreement have been obtained in all the cases treated

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.