• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.793-799
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• 2016

A multi-purpose sensor interface that provides dual-mode operation of fingerprint sensing and physiological signal detection is presented. The dual-mode sensing capability is achieved by utilizing inter-pixel shielding patterns as capacitive amplifier's input electrodes. A prototype readout circuit including a fingerprint panel for feasibility verification was fabricated in a $0.18{\mu}m$ CMOS process. A single-channel readout circuit was implemented and multiplexed to scan two-dimensional fingerprint pixels, where adaptive calibration capability against pixel-capacitance variations was also implemented. Feasibility of the proposed multi-purpose interface was experimentally verified keeping low-power consumption less than 1.9 mW under a 3.3 V supply.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.56-62
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• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.34-37
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• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the inter-metal dielectrics (IMD) layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}m$ POU (point of use) filter, which is depth-type filter and has 80% filtering efficiency for the $1.0{\mu}m$ size particle. In this paper, we studied the relationship between defect generation and pad count to understand the exact efficiency of the slurry filtration, and to find out the appropriate pad usage. Our preliminary results showed that it is impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the flow rate of slurry to overcome depth type filters weak-point, and to install the high spray of de-ionized Water (DIW) with high pressure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.335-338
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• 2003

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-layer dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding $1\;{\mu}m$ in size, which could cause micro-scratch on the wafer surface. In this paper, we have studied aging effect the of CMP sin as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1069-1074
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• 2016

This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.9
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• pp.707-713
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• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was requirdfo the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gest thinner, micro-scratches are becoming as major defects. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}{\textrm}{m}$ point of use (POU) filter, which is depth-type filter and has 80% filtering efficiency for the 1.0${\mu}{\textrm}{m}$ size particle. In this paper, we studied the relationship between defect generation and polished wafer counts to understand the exact efficiency fo the slurry filteration, and to find out the appropriate pad usage. Our experimental results showed that it sis impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate, and to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of depth type filter.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1600-1604
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.111-114
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• 2005

The isolation performance of the S-band single-pole single-throw (SPST) monolithic microwave integrated circuit (MMIC) switch with two different RF-interconnection approaches, microstrip and grounded coplanar waveguide (GCPW) lines, are investigated. On-to-off isolation is improved by 5.8 dB with the GCPW design compared with the microstrip design and additional improvement of 6.9dB is obtained with the coplanar wire-bond interconnection (CWBI) at 3.4 GHz. The measured insertion loss and third-order inter-modulation distortion (IMD3) are less than 2.43 dB over 2.5 CHz $\sim$ 4 GHz and greater than 64 dBc.

• Journal of Electrical Engineering and Technology
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• v.2 no.3
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• pp.294-299
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• 2007

This paper presents a special protection scheme, which was established in the KEPCO (Korea Electric Power Corporation) system, against a critically low voltage profile in a part of the system after a double-circuit tower outage. Without establishing the scheme, the outage triggers the operation of a zone 3 relay and trips the component. This sequence of events possibly leads to a blackout of the local system. The scheme consists of an inter-substation communication network using PITR (Protective Integrated Transmitter and Receiver) for acquisition of the substations' data, and under-voltage load shedding devices. This paper describes the procedure for determining the load shedding in the scheme and the experiences of the implementation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.93-96
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.