• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.5
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• pp.242-248
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• 2002

It is important to develop new effective technologies to increase the interruption capacity and to reduce the size of a UB(Gas Circuit Breakers). Major design parameters such as nozzle geometries and interrupting chamber dimensions affect the cooling of the arc and the breaking performance. But it is not easy to test real GCB model in practice as in theory. Therefore, a simulation tool based on a computational fluid dynamics(CFD) algorithm has been developed to facilitate an optimization of the interrupter. Special attention has been paid to the supersonic flow phenomena between contacts and the observation of hat-gas flow for estimating the breaking performance. However, there are many difficult problems in calculating the flow characteristics in a GCB such as shock wave and complex geometries, which may be either static or in relative motion. Although a number of mesh generation techniques are now available, the generation of meshes around complicated, multi-component geometries like a GCB is still a tedious and difficult task for the computational fluid dynamics. This paper presents the CFD program using CFB-CAD integration technique based on Cartesian cut-cell method, which could reduce researcher's efforts to generate the mesh and achieve the accurate representation of the geometry designed by a CAD tools.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1444-1446
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• 2002

In this paper, we propose a new algorithm to calculate the maximum amount of available resource while preventing the outage to the currently serviced users not only in the home cell but also in adjacent cells. The effect of resource management in adjacent cells is simulated.

• Korean Journal of Optics and Photonics
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• v.18 no.3
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• pp.185-189
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• 2007

A novel technology for CWDM (Coarse Wavelength Division Multiplexer) utilizing a PLC (Planar Lightwave Circuit)-AWG (Arrayed Waveguide Grating) fabrication process is proposed. BPM (Beam Propagation Method) Simulation results on the employed parabolic-horn-type input slab waveguide of AWG and the performance of the 20 nm-channel spacing CWDM with flattened passband are presented. Waveguides of $0.75{\triangle}%$ have been used in this experiment and the insertion loss at the peak wavelength is 3.5 dB for a Gaussian spectrum and is 4.8 dB for a flat-top spectrum. The bandwidth at 3 dB is better than 10 nm and 13 nm for Gaussian and flat-top spectra, respectively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2002.11a
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• pp.281-286
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• 2002

An existent hoist drive system is using each different drive equipment in control of Hoisting, traveling(T/L), traversing(T/S) driving, so there are much energy losses because of excessive weight. Also, power circuits are using relay contact, so working environment are frequent secession accident etc.. by shock on unfavorable condition, and there is danger of safety accident, maintenance has frequent problem and so on. To solve these problem, it is integrated each driving power supply in drive system for hoist control and drive, utility power supply etc.. by single device in this research. The power circuit is consisted of non-contact circuit applying to bidirectional voltage controller circuit using thyristor that is power semiconductor switching device

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.11B no.3
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• pp.112-118
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• 2001

In the near future, the voltage of power system for passenger vehicle will be changed to 42V from existing 14V./ Because of increasing power and voltage ratings used in the vehicle the motor drive system has high switching dv/dt and it generates electromagnetic interference (EMI) To solve these problems multi-level inverter system may be used The feature of multi-level inverter is the output voltage to be synthesized from several levels of voltage Because of this feature high switching dv/dt and EMI can be reduced in the multi-level inverter system But as the number of level is increased manufacturing cost is getting expensive and system size is getting large. Because of these disadvantages the application of multi-level inverter has been restricted only to high power drives. The method to reduce manufacturing cost and system size is to integrate circuit of multi-level inverter into a few chips But isolated power supply and signal isolation circuit using transformer or opto-coupler for drive circuit are obstacles to implement the integrated circuit (IC) In this paper a drive circuit of 4-level inverter suitable for integration to hybrid or one chip is proposed In the proposed drive circuit DC link voltage is used directly as the power source of each gate drive circuit NPN transistors and PNP transistors are used to isolate to transfer the control signals. So the proposed drive circuit needs no transformers and opto-couplers for electrical isolation of drive circuit and is constructed only using components to be implemented on a silicon wafer With th e proposed drive circuit 4- level inverter system will be possible to be implemented through integrated circuit technology Using the proposed drive circuit 4- level inverter system is constructed and the validity and characteristics of the proposed drive circuit are proved through the experiments.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.42-49
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• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Journal of Power Electronics
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• v.12 no.3
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• pp.439-447
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• 2012

In this paper, an input-series auxiliary power supply scheme is proposed, which is suitable for high input voltage and multiple-output applications. The power supply scheme is based on a two-transistor forward topology, all of the series modules have a common duty ratio, all the switches are turned on and off simultaneously, and the whole circuit has a single power transformer. It does not require an additional controller but still achieves efficient input voltage sharing (IVS) for each series module through its inherent transformer-integration strategy. The IVS process of this power supply scheme is analyzed in detail and the design considerations for the related parameters are given. Finally, a 100W multiple-output auxiliary power supply prototype is built, and the experimental results verify the feasibility of the proposed scheme and the validity of the theoretical analysis.