• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.209-216
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• 2003

As the interest in the wireless internet services is increasing recently, the related technology development is in active progress. According to WAP (Wireless Application Protocol) specification which is currently considered as one of the most powerful international standardizations, mobile terminal and WAP server are supposed to communicate through WAP Gateway. This paper is about the design and implementation of IWAP platform where WAP Gateway and Server are integrated and supported based on Linux. The proposed WAP platform broadly consists of four modules like WAP Gateway, JAVA based Server development environment, WML Tool-Kit, and MUL (Management User Interface) and for bearer network, SMSC (Short Message Service Center) and CSD (Circuit Switched Data) router are considered.

• Journal of Radiation Protection and Research
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• v.45 no.1
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• pp.35-44
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• 2020

Background: Cadmium zinc telluride (CZT) is a promising material because of a high detection efficiency, good energy resolution, and operability at room temperature. However, the cost of CZT dramatically increases as its size increases. In this study, to achieve a large effective volume with relatively low cost, an array structure comprised of individual virtual Frisch-grid CZT detectors was proposed. Materials and Methods: The prototype consisted of 2 × 2 CZTs, a holder, anode and cathode printed circuit boards (PCBs), and an application-specific integrated circuit (ASIC). CZTs were used and the non-contacting shielding electrode method was applied for virtual Frisch-grid effect. An ASIC was used, and the holder and the PCBs were fabricated. In the current system, because the CZTs formed a common cathode, a total of 5 channels were assigned for data processing. Results and Discussion: An experiment using ¹³⁷Cs at room temperature was conducted for 10 minutes. Energy and timing information was acquired and the depth of interaction was calculated by the timing difference between the signals of both electrodes. Based on obtained three-dimensional position information, the energy correction was carried out, and as a result the energy spectra showed the improvements. In addition, a Compton image was reconstructed using the iterative method. Conclusion: The virtual Frisch-grid CZT detector based on the array structure was developed and the energy spectra and the Compton image were successfully acquired.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.639-647
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• 1990

Dynamic time warp(DTW) needs for interative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at the real time recognition design which enables large dictionary hardware realization using DTW algorithm. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. We have accomplisehd circuit design and verification for the MIN blocks, and performed MIN layout and DRC(design rule check) using 3um CMOS N-Well rule base.ing 3um CMOS N-Well rule base.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1175-1182
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• 2010

In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.8
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• pp.112-119
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• 1996

Among the various type of accelerometer, the servo rebalancing type accelermoter can be suitable for Inertial Navigation System, because of its high sensitivity and good response in low frequency. In this paper, we proposed a new technology to control inductive tuype accelerometer utilizing digital PWM method. The new developed digital PWM control has special design scheme for transmitting measurement value to outer device in its servo ollp. So it has no quantized error of transforming outputs of sensors to digital domain. The quantized error may make serious problem in INS system, because outputs of sensor are integrated once or twice by digital computer and it happens every sensor reading times. Therefore, in order to get the accurate information such as displacement, it is necessary to measure accurately the input current. In addition, Digital Signal Processing needs digital data transmission, digital PWM method is adaptive for this purpose. We realized a practical circuit for digital PWM control, analyzed the stability of the circuit, and designed the controller etc. In this study, we solved many practical problem for this application, and got out good results.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Korean Journal of Audiology
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• v.24 no.4
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• pp.174-179
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• 2020

Background and Objectives: The integration of auditory-visual speech information improves speech perception; however, if the auditory system input is disrupted due to hearing loss, auditory and visual inputs cannot be fully integrated. Additionally, temporal coincidence of auditory and visual input is a significantly important factor in integrating the input of these two senses. Time delayed acoustic pathway caused by the signal passing through digital signal processing. Therefore, this study aimed to investigate the effects of hearing loss and hearing aid digital delay circuit on sound-induced flash illusion. Subjects and Methods: A total of 13 adults with normal hearing, 13 with mild to moderate hearing loss, and 13 with moderate to severe hearing loss were enrolled in this study. Subsequently, the sound-induced flash illusion test was conducted, and the results were analyzed. Results: The results showed that hearing aid digital delay and hearing loss had no detrimental effect on sound-induced flash illusion. Conclusions: Transmission velocity and neural transduction rate of the auditory inputs decreased in patients with hearing loss. Hence, the integrating auditory and visual sensory cannot be combined completely. Although the transmission rate of the auditory sense input was approximately normal when the hearing aid was prescribed. Thus, it can be concluded that the processing delay in the hearing aid circuit is insufficient to disrupt the integration of auditory and visual information.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.2
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• pp.55-59
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• 2004

Throughout manufacturing processes, pulse shaping is required for material processing and it is regarded as an important (actor according to the specific characteristics of materials. Therefore, this study suggests a highly appropriate pulse shaping technique using a multi-switching method. This is a pulse superposition method in which one flash lamp can consecutively turn on by the double switching of the discharging system. It is possible to construct a variety of pulse shapes and pulse widths by the consecutive trigger of the silicon-controlled rectifiers (SCR) of a PIC (program integrated circuit) one-chip microprocessor. The use of this technique can provide a number of advantages to people who require suitable pulse shaping for particular applications such as welding, cutting, and drilling.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.48-51
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• 1997

This paper presents the algorithm of FIC inspection in chip mounter. When device is mounted on the PCB, it is impossible to get zero defects since there are many problems which can not be predicted. Of these problems, devices with bent corner leads due to mis-handling and which are not placed at a given point measured along the axis are principal problem in SMT(Surface Mounting Technology). In this paper, we proposed a new algorithm based on the Radon transform which uses a projection to inspect the FIC(Flat Integrated Circuit) device and compared this method with other algorithms. We measured the position error and applied this algorithm to our image processing board which is characterized by line scan camera. We compared speed and accuracy in our board.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.10-16
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• 2016

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).