• Title/Summary/Keyword: Input power level

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Design and Fabrication of 5 GHz Band MMIC Power Amplifier for Wireless LAN Applications Using Size Optimization of PHEMTs (PHEMT 크기 최적화를 이용한 무선랜용 5 GHz 대역 MMIC 전력증폭기 설계 및 제작)

  • Park Hun;Hwang In-Gab;Yoon Kyung-Sik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.6A
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    • pp.634-639
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    • 2006
  • In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

Parameterized FFT/IFFT Core Generator for ODFM Modulation/Demodulation (OFDM 변복조를 위한 파라메터화된 FFT/IFFT 코어 생성기)

  • Lee, J.W.;Kim, J.H.;Shin, K.W.;Baek, Y.S.;Eo, I.S.
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.659-662
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    • 2005
  • A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

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The Development of EMG-based Powered Wheelchair Controller for Users with High-level Spinal Cord Injury using a Proportional Control Scheme (중증 장애인을 위한 근전도 기반 비례제어 방식의 전동 휠체어 제어기 개발)

  • Song, Jae-Hoon;Han, Jeong-Su;Oh, Young-Joon;Lee, He-Young;Bien, Zeung-Nam
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.6-8
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    • 2004
  • The objective of this paper is to develop a powered wheelchair controller based on EMG for users with high-level spinal cord injury using a proportional control scheme. An advantage of EMG is relative convenience of acquisition by a surface electrode to users. Direction information can be easily extracted from two EMG channels and force information can be acquired by proportional relationship between the amplitude of EMG and user's power, respectively. Pattern classification algorithm is a threshold method with a supervised learning process. Furthermore, the emergency situation can be avoided using an interrupt function. We evaluated the performance of powered wheelchair controller by navigating a pre-defined path with three non-handicapped people. The results show the feasibility of EMG as an input interface for powered wheelchair and other devices for the seriously disabled.

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Throughput Based Study of UWB Receiver Modem Parameters

  • Choi, Byoung-Jo
    • Journal of information and communication convergence engineering
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    • v.6 no.2
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    • pp.158-163
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    • 2008
  • The MB-OFDM based UWB communication system is a personal area network specification aiming to provide 480Mbps peak data rate over 528 MHz spectrum. As the corresponding baseband modem operates at high clock rate, its complexity should be optimized for low power consumption. A set of modem design parameters is suggested including the AD bit width, the clipping level and the quantization level at the Viterbi decoder input as well as the trace-back depth of the Viterbi decoder. The data throughput is used to evaluate the performance of the receiver and a recommended set of design parameter values is presented to aid efficient modem implementation.

Performance Analysis on the Variable Speed Scroll Compressor with Operating Conditions (가변속 스크롤 압축기의 운전조건의 변화에 따른 성능 해석)

  • 박홍희;박윤철;김용찬
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.12 no.7
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    • pp.649-658
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    • 2000
  • Thermodynamic modeling of low-pressure scroll compressor was developed by combining continuity and energy conservation equation. Suction gas heating was considered using energy balance inside the low pressure shell. Pressure, temperature and mass of refrigerant-22 as a function of orbiting angle were calculated by solving the governing equations using fourth order Rung-Kutta scheme. Motor efficiency was taken by experiments with a variation of frequency. The developed model was applied to the analysis of an inverter driven scroll compressor with a variation of frequency, pressure ratio and operating conditions. The model was verified with the experimental results at the same operating conditions. The developed model was adequate to predict performance of the inverter driven scroll compressor as a function of operating conditions. Calculated parameters from the model were discharge temperature, mass flow rate, power input, COP, and thermodynamic properties with respect to orbiting angle. To enhance the performance of a scroll compressor, it is essential to diminish leakage at low frequency level and improve the mechanical efficiency at high frequency level.

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A Multilevel Inverter Using DC Link Voltage Combination (DC링크 전압 조합을 이용한 멀티 레벨 인버터)

  • Joo S.Y.;Lee J.H.;Kang F.S.;Kim C.U.;Park S.J.
    • Proceedings of the KIPE Conference
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    • 2003.07b
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    • pp.621-624
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    • 2003
  • In this paper, a novel multilevel inverter using DC-Link voltage combination is presented to reduce the harmonics of output voltage without the output filter inductor. The proposed multilevel inverter can generate 27-level output voltage. It employs three H-bridge cells which consist of single phase full-bridge inverter module. As well as, it can make continuous output voltage level employing the properly three DC-Link voltage ratio. The validity of the proposed inverter is verified through the experimental result using a prototype which can generate a 110[Vac], 60[Hz] output voltage from 12[Vdc], 36[vdc], and 108[Vdc] input voltages

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GEO Satellite Magnetic Momentum Assessment

  • Yang, Jeong-Hwan;Kim, Eui-Chan;Koo, Ja-Chun;Lee, Sang-Kon
    • The Bulletin of The Korean Astronomical Society
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    • v.37 no.2
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    • pp.182.2-182.2
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    • 2012
  • If the satellite has the magnetic material or magnetic moment, the satellite is affected by the earth magnetic field by the space environment in Geostational orbit. The aim of this paper is to assess the satellite magnetic momentum which is an input to ADCS(Altitude Determination Control Subsystem) analyses to assess spurious torques. The magnetic momentum at satellite level is due to magnetic momentum generated by each unit which is due to internal currents circulation or to the presence of magnetic components. Also the magnetic momentum at satellite level is due to circulation of the DC supply current from PSR(Power Supply Regulator) to each unit. As introducing the intrinsic contribution of each unit and the magnetic moment based on the current return through the structure, this paper assess the satellite magnetic moment.

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Design Guidelines for a Capacitive Wireless Power Transfer System with Input/Output Matching Transformers

  • Choi, Sung-Jin
    • Journal of Electrical Engineering and Technology
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    • v.11 no.6
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    • pp.1656-1663
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    • 2016
  • A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

Modeling and Analysis of Power Piezoelectric Transformer and Its Application to Fluorescent Lamp Ballasts (압전 변압기의 모델링과 형광등 안정기회로에의 응용)

  • Choe, Seong-Jin;Lee, Gyu-Chan;Jo, Bo-Hyeong
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.48 no.7
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    • pp.376-383
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    • 1999
  • The piezoelectric transformer (PT) is an electro-mechanical device that transfers electrical energy through a mechanical vibration. In this paper, a PT operating in the contour vibration mode is introduced for an application of fluorescent lamp ballast. Utilizing its inherent characteristics of the LC resonator and a high voltage gain to ignite the lamp in light load condition, an investigation of a power piezoelectric transformer as a potential component for a fluorescent lamp ballast is discussed. PT is easy to be produced in mass and reduces the cost of the ballast. The modified equivalent circuit model of the PT considering the operating current level is derived to design the fluorescent lamp ballast. This model describes the voltage gain of the PT in wide load variations and various input current levels. The experimental and simulation results are provided to verify theoretical analysis. The power capacity of the currently developed PT is relatively low (15W), but it can be increased by adopting a multi-layer structure and is currently under investigation. It is also possible to parallel the PT for higher power processing.

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Design of the Inverter Motor Drive System Applied to PFC using Interleaving Method (인터리빙 PFC를 적용한 모터구동 인버터 시스템 설계)

  • Yoon, Seong-Sik;Choi, Hyun-Eui;Kim, Tae-Woo;Ahn, Ho-Kyun;Park, Seung-Kyu;Yoon, Tae-Sung;Kwak, Gun-Pyoung
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.4
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    • pp.14-19
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    • 2010
  • In this paper, using interleaved power factor correction how to improve the inverter efficiency studied. Interleaved method can reduce the conduction losses and the inductor energy. Generally, critical conduction mode (CRM) boost PFC converter used low power level because of the high peak currents. if you use the interleaved mode, CRM PFC can be used medium or high power application. interleaved CRM PFC can reduce current ripple for higher system reliability and size of buck capacitor and EMI filter size. Interleaved CRM PFC that is installed in front of inverter can maintain the constant voltage regardless of the input voltage.