• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권9호
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• pp.3663-3679
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• 2020

Scheduling plays a dynamic role in cloud computing in generating as well as in efficient distribution of the resources of each task. The principle goal of scheduling is to limit resource starvation and to guarantee fairness among the parties using the resources. The demand for resources fluctuates dynamically hence the prearranging of resources is a challenging task. Many task-scheduling approaches have been used in the cloud-computing environment. Security in cloud computing environment is one of the core issue in distributed computing. We have designed a deep learning-based security model for scheduling tasks in cloud computing and it has been implemented using CloudSim 3.0 simulator written in Java and verification of the results from different perspectives, such as response time with and without security factors, makespan, cost, CPU utilization, I/O utilization, Memory utilization, and execution time is compared with Round Robin (RR) and Waited Round Robin (WRR) algorithms.

• International Journal of Internet, Broadcasting and Communication
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• 제12권1호
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• pp.144-150
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• 2020

Reinforcement learning is a technology that can present successful and creative solutions in many areas. This reinforcement learning technology was used to deploy containers from cloud servers to fog servers to help them learn the maximization of rewards due to reduced traffic. Leveraging reinforcement learning is aimed at predicting traffic in the network and optimizing traffic-based fog computing network environment for cloud, fog and clients. The reinforcement learning system collects network traffic data from the fog server and IoT. Reinforcement learning neural networks, which use collected traffic data as input values, can consist of Long Short-Term Memory (LSTM) neural networks in network environments that support fog computing, to learn time series data and to predict optimized traffic. Description of the input and output values of the traffic-based reinforcement learning LSTM neural network, the composition of the node, the activation function and error function of the hidden layer, the overfitting method, and the optimization algorithm.

• 전기의세계
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• 제21권4호
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• pp.39-44
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• 1972

This paper describes a new approach for minimizing working memory spaces without loosing too much amount of computing time in the analysis of power system faults. This approach requires the decomposition of alrge power system into several small groups of subsystems, forms individual bus impedance matrics, store them in the auxiliary memory, later assembles them to the original total system by algorithms. And also the approach uses techniques for diagonalizing primitive impedances and expanding the system bus impedance matrices by adding a fault bus. These scheme ensures a remarkable savings of working storage and continous computations of fault currents and voltages with the voried fault locations.

• Journal of Computing Science and Engineering
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• 제3권3호
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• pp.181-194
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• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• International Journal of Internet, Broadcasting and Communication
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• 제13권3호
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• 한국산업융합학회 논문집
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• 제24권1호
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• 한국차세대컴퓨팅학회논문지
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• 제13권3호
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• pp.26-33
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• 2017

최근 클라우드 플랫폼을 효율적으로 사용하기 위한 컨테이너 기술들이 주목을 받고 있다. 컨테이너 가상화 기술은 기존 하이퍼바이저와 비교하였을 때 이식성이 뛰어나고 집적도가 높다는 장점을 가지고 있다. 하지만 컨테이너 가상화 기술은 하나의 커널을 공유하여 복수개의 인스턴스를 구동하는 운영체제 레벨의 가상화 기술을 사용하기 때문에 인스턴스 간 공유 자원 요소가 많아져 취약성 또한 증가하는 보안 문제를 가지고 있다. 컨테이너는 컴퓨팅 자원의 효율적 운용을 위해 호스트 운영체제의 라이브러리를 공유하는 특성으로 인해 공격자는 커널의 취약점을 이용하여 호스트 운영체제의 루트 권한 획득 공격이 가능하다. 본 논문에서는 컨테이너가 사용하는 특정 메모리 영역의 변화를 감지하고, 감지 시에는 해당 컨테이너의 동작을 중지시키는 메모리 트랩 기법을 사용하여 컨테이너 내부에서 발생되는 호스트 운영체제의 루트 권한 탈취 공격을 효율적으로 탐지 및 대응하기 위한 프레임워크를 제안한다.

• 방송공학회논문지
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• 제28권1호
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• pp.42-54
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• 2023

방대한 홀로그램 데이터를 디지털 형식으로 압축하는 것은 중요한 문제이다. 특히, 상용화를 위해 위상 전용 홀로그램의 압축에 관한 연구가 주목된다. 자연 영상에 최적화된 기존 표준 압축 기술은 위상 신호를 압축하는데 적합하지 않으며, 위상 신호에 대해 최적화 가능한 신경망 기반 압축 기술은 좋은 성능을 기대할 수 있으나 고해상도 홀로그램 데이터를 학습하는 데 메모리 문제가 존재한다. 본 논문에서는 메모리 문제를 해결할 수 있는 학습 가능한 신경망 기반의 블록 단위 압축 기술을 위상 전용 홀로그램에 적용해봄으로써 블록 기반이라는 동일 조건 내에서도 제안 방식이 표준 코덱보다 상당한 성능향상을 보일 수 있음을 밝혔다. 신경망 기반의 블록 단위 압축은 기존 코덱과의 호환성을 제공할 수 있으며, 메모리 문제를 해결하는 동시에 위상 전용 홀로그램 압축에 대해 월등히 좋은 성능을 보일 수 있다.