• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.157-160
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• 2000

본 논문에서는 DVCR용 2-4-8 DCT core의 VSIA(Virtual Socket Interface Allience) 2.2 compliant IP의 구현에 대하여 기술한다. 본 논문에서 기술한 2-4-8 DCT/IDCT core는 Soft IP이며, VSIA의 deliverable document ver. 2.2에서 정의한 Soft-IP에 대한 72가지의 필수 항목, 조건부 필수 항목, 권고 항목 등의 전달물을 각 DWG(Development Working Group)의 사양에서 정의하고 있는 규격에 맞추어 가공하였다. 또한 본 논문에서는 Soft-IP에 대한 VSIA 권고안 및 VSIA deliverable list에 대하여 기술하고, VSIA compliant IP화를 위한 방법에 대하여 설명하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.307-310
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• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.

• Journal of KIISE:Information Networking
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• v.30 no.3
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• pp.424-436
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• 2003

In this paper, we propose the Centroid-based Backbone Core Tree(CBCT) generation algorithm for the shared tree-based IP multicasting. The proposed algorithm is based on the Core Based Tree(CBT) protocol. Despite the advantages over the source-based trees in terms of scalability, the CBT protocol still has the following limitations; first, the optimal core router selection is very difficult, and second, the multicast traffic is concentrated near a core router. The Backbone Core Tree(BCT) protocol, as an extension of the CBT protocol has been proposed to overcome these limitations of the CBT Instead of selecting a specific core router for each multicast group, the BCT protocol forms a backbone network of candidate core routers which cooperate with one another to make multicast trees. However, the BCT protocol has not mentioned the way of selecting candidate core routers and how to connect them. The proposed CBCT generation algorithm employs the concepts of the minimum spanning tree and the centroid. For the performance evaluation of the proposed algorithm, we showed the performance comparison results for both of the CBT and CBCT protocols.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.113-124
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• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• Annual Conference of KIPS
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• 2002.11b
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• pp.1281-1284
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• 2002

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32 비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 톤 발생 및 음성신호 접속기능과 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• ETRI Journal
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• v.25 no.5
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• pp.305-314
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• 2003

In this paper, we present a soft IP compiler for the Reed-Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed-Solomon decoder with appropriate sub-architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.34-42
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• 2012

This paper analyses the energy saving basic power models in core IP networks, and proposes the adaptive buffer and burst scheme which is a possible energy saving method, and its implementation algorithm in core IP networks. Especially this paper describes the adaptive buffer and burst scheme dynamically varying the buffering interval B according to the input traffic volume of ingress router, and explains the operation principle of proposed scheme. This method is to adjust the buffering interval B according to input traffic volume of ingress router, that is increasing the interval B when input traffic volume is low, and decreasing the interval B when input traffic volume is high between some given interval regions. This method can gets the high energy saving effect as decreasing the transition number of idle/active in networks when input traffic volume is low, and decreasing the transition number of idle/active by the continuous of burst packets in transit router when input traffic volume is high. This paper shows the increasing of asleep rate for the energy saving of core IP networks and confirms the energy saving of core IP networks by the computer simulation. We confirmed that proposed method can be save the energy of IP networks by properly trade off network performances.

• The KIPS Transactions:PartC
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• v.12C no.5 s.101
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• pp.687-694
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• 2005

In ATM and W networks, high Priority Packets should be selectively favored over low Priority Packets in case of congestion. For this purpose, we introduce a space priority policy for ATM nodes in this paper which is very similar to the weighted core-stateless fair queueing(WCSFQ) in IP nodes. We also analyze the loss probabilities for different classes of cells for MMPP/D/1/K with a threshold level, and discuss the numerical results. The numerical results illustrate that the WCSFQ scheme can be used to support the differentiated services in ATM or IP nodes.

• Journal of Advanced Navigation Technology
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• v.12 no.6
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• pp.591-597
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• 2008

With the established voice service, the data service is increasing in the field of mobile telecommunications in these days. Also, the data service develops into the form of multimedia service which combines various media. However, it is limited to provide QoS(Quality of Service) for the multimedia using the established network which manages all the data in sam: rule. So, this paper suggests the network architecture which assures QoS of multimedia data by applying MPLS(Multi-Protocol Label Switching) to the core network. Especially, we analyze the efficiency of the network combining Mobile IP network based on the WLAN(Wireless LAN) and core network based on MPLS through by network simulations using QualNet.