• Title/Summary/Keyword: IIP

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Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

  • Lee, Hyun Kook;Choi, Woo Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.551-555
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    • 2013
  • Linearity characteristics of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) have been compared with those of high-k-only and $SiO_2$-only TFETs in terms of IIP3 and P1dB. It has been observed that the optimized HG TFETs have higher IIP3 and P1dB than high-k-only and $SiO_2$-only TFETs. It is because HG TFETs show higher transconductance ($g_m$) and current drivability than $SiO_2$-only TFETs and $g_m$ less sensitive to gate voltage than high-k-only TFETs.

Post-Linearization of Differential CMOS Low Noise Amplifier Using Cross-Coupled FETs

  • Kim, Tae-Sung;Kim, Seong-Kyun;Park, Jin-Sung;Kim, Byung-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.283-288
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    • 2008
  • A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

Design of 24GHz Low Noise Amplifier for Automotive Collision Avoidance Radar (차량 추돌 예방 레이더용 24GHz 저잡음증폭기 설계)

  • Choi, Seong-Kyu;Lee, Jae-Hwan;Kim, Sung-Woo;Ryu, Jee-Youl;Noh, Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.829-831
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    • 2012
  • 본 논문은 차량 추돌 예방 레이더용 고 이득 저전력 저잡음 특성을 가진 24GHz 저잡음 증폭기(LNA)를 제안한다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 증폭기의 전압 이득을 향상시키기 위해 2단 캐스코드 구조로 구성되어 있다. 제안한 저잡음 증폭기는 최근 발표된 연구결과에 비해 41dB의 가장 높은 전압이득과 3.7dB의 가장 낮은 잡음지수 및 2.8dBm의 가장 우수한 IIP3 특성을 각각 보였다.

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Millimeter-Wave High-Linear CMOS Low-Noise Amplifier Using Multiple-Gate Transistors

  • Kim, Ji-Hoon;Choi, Woo-Yeol;Quraishi, Abdus Samad;Kwon, Young-Woo
    • ETRI Journal
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    • v.33 no.3
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    • pp.462-465
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    • 2011
  • A millimeter-wave (mm-wave) high-linear low-noise amplifier (LNA) is presented using a 0.18 ${\mu}m$ standard CMOS process. To improve the linearity of mm-wave LNAs, we adopted the multiple-gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate-source bias at the last stage of LNAs, third-order input intercept point (IIP3) and 1-dB gain compression point ($P_{1dB}$) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.

Design of a Low Noise Amplifier for Wireless LAN (무선 근거리 통신망용 저잡음 증폭기의 설계)

  • 류지열;노석호;박세현
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1158-1165
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    • 2004
  • This paper describes the design of a two stage 1V power supply SiGe Low Noise Amplifier operating at 5.25㎓ for 802.lla wireless LAN application. The achieved performance includes a gain of 17㏈, noise figure of 2.7㏈, reflection coefficient of 15㏈, IIP3 of -5㏈m, and 1-㏈ compression point of -14㏈m. The total power consumption of the circuit was 7㎽ including 0.5㎽ for the bias circuit.

Broadband CMOS Single-ended to Differential Converter for DVB-S2 Receiver Tuner IC (DVB-S2 수신기 튜너용 IC의 광대역 CMOS 단일신호-차동신호 변환기)

  • Shin, Hwa-Hyeong;Kim, Nam-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.185-185
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    • 2008
  • This paper describes the broadband SDC (Single-ended to Differential Converter) for Digital Video Broadcasting-Satellite $2^{nd}$ edition (DVB-S2) receiver tuner IC. It is fabricated by using $0.18{\mu}m$ CMOS process. In order to obtain high linearity and low phase mismatch, the broadband SDC (Single-ended to Differential Converter) is designed with current mirror structure and cross-coupled capacitor and current source binding differential structure at VDD. The simulation result of SDC shows IIP3 of 11.9 dBm and IIP2 of 38 dBm. It consumes 5mA current with 2.7V supply voltage.

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Analysis and Optimization of Cross-Modulation Noise in CDMA Cellular RF System (CDMA 셀룰러 RF 시스템에서 교차변조 잡음 레벨 분석 및 최적화)

  • 곽준호;김학선
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.6A
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    • pp.397-404
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    • 2003
  • In this paper, we have analyzed the level of cross-modulation noise required for CDMA mobile station and proposed a guideline for optimum design. From the analysis, the level of cross-modulation noise is determined by the system's noise figure(NF) and VCO's phase noise and there is a trade-off relationships between them. In addition, we have determined the value of LNA's IIP3 and duplexer's isolation to satisfy the above level in designing the system. Therefore, this paper will give a guideline for a selection of components in designing cdma2000 mobile station.

Design of Emergency Destruction System for Long-range Surface-to-Air Missile Flight Test (장거리 대공 유도탄 비행 시험을 위한 안전종료판단시스템 설계)

  • Eunyoung Noh
    • Journal of the Korea Institute of Military Science and Technology
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    • v.27 no.4
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    • pp.466-473
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    • 2024
  • An Emergency Destruction System is inevitable for ensuring safety both at sea and in populated areas, particularly during emergency detonations triggered by abnormal missile flight or upon mission completion. This paper introduces a novel method for developing an Emergency Destruction System capable of precisely calculating the Instantaneous Impact Point(IIP) during high-speed, maneuverable long-range surface-to-air missile flight tests. The Emergency Destruction System designed for long-range surface-to-air missile flight tests generates impact position tables that meticulously incorporate wind errors and navigation equations based on the Earth's ellipsoidal model. Factors such as the Coriolis effect and the direction of the gravitational acceleration vector are accounted for, significantly enhancing the accuracy of IIP determination amidst highly variable missile speed and attitude.

A Feedback Wideband CMOS LNA Employing Active Inductor-Based Bandwidth Extension Technique

  • Choi, Jaeyoung;Kim, Sanggil;Im, Donggu
    • Smart Media Journal
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    • v.4 no.2
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    • pp.55-61
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    • 2015
  • A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

Design and Implementation of a Near Zero IF Sub-harmonic Cascode FET Mixer for 2.4 GHz WLL Base-Station (Near Zero IF를 갖는 2.4 GHz WLL 기지국용 하모닉 Cascode FET 혼합기 설계 및 제작)

  • Lee, Hyok;Jeong, Youn-Suk;Kim, Jeong-Pyo;Choi, Jea-Hoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.5
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    • pp.472-478
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    • 2003
  • In this paper, a near zero If mixer was designed in cascode structure by using two single-gate FETs. Since it is driven by the second order harmonic of LO signal, a sub-harmonic cascode FET mixer has good LO-RF port isolation characteristic. In order to solve DC offset of a homodyne system, near zero If is used instead of zero If and the mixer is driven by sub-harmonic of LO signal. As RF input power was -30 dBm and LO power was 6 dBm, the designed mixer had 6.7 dB conversion gain, 8.4 dB noise figure, 31.5 dB LO-RF port isolation, -1.9 dBm lIP3 and -2.8 dBm IIP2.