• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.393-396
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• 1999

A circuit model of silicon substrate coupling for CMOS RF-IC design is developed. Its characteristics are analyzed by using a simple RC mesh model in order to investigate substrate coupling. The coupling effects due to the substrate were characterized with substrate resistivity, oxide thickness, substrate thickness. and physical distance. Thereby the silicon substrate effects are analytically investigated and verified with simulation. The analysis and simulation of the model have excellent agreements with MEDICI(2D device simulator) simulation results.

• 대한전자공학회논문지SD
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• 제44권4호
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• pp.32-42
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• 2007

[ $0.35{\mu}m$ ]twin-well non-epitaxial CMOS 공정에서의 substrate noise에 의한 아날로그 회로의 성능 저하를 예측하기 위하여 substrate 저항을 모델링하였다. Substrate 저항 모델 방정식은 P+ guard-ring isolation에 적용되어 측정값과 일치함을 확인하였다. Substrate 저항을 네 가지 형태로 구분하고 각각에 대하여 semi-empirical 모델 방정식을 확립하여, 측정값과 비교하여 rms 오차가 10% 미만이 되었다. 이 substrate 저항 모델을 guard-ring에 의한 isolation 구조에 적용하기 위하여 모델 방정식과 ADS(Advanced Design System) 회로 시뮬레이션에 의한 결과와 Network Analyzer의 측정 결과를 비교하였고, 비교적 잘 일치함을 확인하였다.

• 한국레이저가공학회지
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• 제15권4호
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• pp.16-19
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• 2012

Due to the fact that the dimensions of circuit lines of IC substrates have been forecast to reduce rapidly, engraving the circuit line patterns with laser has emerged as a promising alternative. To engrave circuit line patterns in an IC substrate, we used a projection ablation technique in which a metal (INVAR) mask and a DPSS UV laser instead of an excimer laser are used. Results showed that the circuit line patterns engraved in the IC substrate have a width of about 15um and a depth of $13{\mu}m$. This indicates that the projection ablation with a metal mask and a DPSS UV laser could feasibly replace the semi-additive process (SAP).

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.127-128
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• 2012

• 대한전자공학회논문지
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• 제13권3호
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• pp.22-27
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• 1976

집적회로(I.C)의 설계에 있어서는 평수구조의 변형만이 가능하므로 여러가지 다른 트랜지스터 (Transistor)가 결합하여 하나의 특정한 기능을 발휘하게 되는 선형회로에는 회로의 설계와 동시에 사용될 적층(EPI)의 비저항 및 두께와 적층(EPI)과 기판 사이에 삽입되는 이침층(Buried Layer)의 구조 등을 정확히 알아야 한다. 본 연구에서는 집적회로의 동작전압과 적층 두께및 비저항과의 관계를 실측치와 비교분석 하였고 이 결과를 선형 집적회로 설계에 이용 가능하도록 도시하였다. For linear IC design, one has to know the epi thickness, resistivity, and structure of buried island inserted between epi and substrate because the mask structure can only be changed for linear IC consisted of various type of transistors to be made for desired specific function. The interrelation of IC operational and saturation voltages with epi resistivity, theckness and divice structure are studied and presented in graphic forms so that IC design engineers can utilize them.

• Journal of Welding and Joining
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• 제18권6호
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• pp.96-101
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• 2000

Sintered alumina ceramic substrate has been used for the insulating substrate for thick Hybrid IC owing to its cheapness and good insulating properties. Some of thick HIC's are important to eliminate the heat emitted from the parts that are mounted on the ceramic substrate. Sintered ceramic substrate can not transfer and emit the heat efficiently. It's been tried to do plasma spray coating of alumina ceramic on the metal substrates that have a good heat emission property. The most important properties to commercialize this ceramic coated metal substrate are surface roughness and deposition efficiency. In this study, plasma spray coating parameters are optimized to minimize the surface roughness and to maximize the deposition efficiency using Taguchi experimental method. By this optimization, the deposition efficiency was greatly improved from 35% at the frist time to 75% finally.

• 한국광학회:학술대회논문집
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• 한국광학회 2008년도 하계학술발표회 논문집
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• pp.325-326
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• 2008

• 한국레이저가공학회지
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• 제14권1호
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• pp.14-18
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• 2011

Semiconductor industry demands decrease in line/space dimensions of IC substrates. Particularly for IC substrates for CPU, line/space dimensions below $10{\mu}m/10{\mu}m$ are expected to be used in production since 2014. Conventional production technologies (SAP, etc.) based on photolithography are widely agreed to be reaching capability limits. To address this limitation, the embedded circuit fabrication technology using laser ablation has been recently developed. In this paper, we used a nanosecond UV laser and a picosecond UV laser to fabricate embedded circuit patterns into a buildup film with $SiO_2$ powders for IC substrate. We conducted SEM and EDS analysis to investigate surface quality of the embedded circuit patterns. Experimental results showed that due to higher recoil pressure, picosecond UV laser ablation of the buildup film generated a better surface roughness.

• ETRI Journal
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• 제32권2호
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• pp.327-329
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• 2010

A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

• ETRI Journal
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• 제38권4호
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• pp.645-653
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• 2016

This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.