• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.73-76
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• 2002

In this paper we present an integrated Hail sensor It for fan motors, fabricated in industrial bipolar process. As a discrete Hall sensor and signal processing circuitry In the fan motor system were Integrated into single chip a temperature dependence of Hall sensitivity and Hall offset voltage can be compensated and cancelled by on-chip circuitry. We Propose a novel temperature compensation of Hall sensitivity with negative temperature coefficient (TC) using the differential amplifier gain with Positive TC. After a package of the chip was sealed using a plastic Package 20 Pins, the thermal and magnetic characteristics were investigated. The obtained experimental results are in agreement with analytical predictions and have more excellent performance than\ulcorner conventional the fan motor system using discrete Hall sensor.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권7호
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• pp.351-363
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• 2001

This paper presents an experimental investigation on the heat trensfer characteristic of micro pipe (MHP) array with 38 triangular microgrooves. A heat pipe is an effective heat exchanger operating without external power. The heat pipe transfers heat by means of the latent heat of vaporization and two-phase fluid flow driven by the capillary force. The overall size of the MHP array can be put undermeath a microelectonic die and integrated into the electrronic package of a microelectronin device to dissipate the heat from the die. The MHP array is fabricated by micromachining with a silicon wafer and a glass substrate. The MHP was filled with water and sealed. The experimental results show the temperature decrease of 12.1$^{\circ}C$ at the evaporator section for the input power of 5.9 W and the improvement of 28% in the heat transfer rate.

• 한국세라믹학회지
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• 제26권6호
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• pp.829-835
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• 1989

Devitrifing solder glasses in a specific group of glass ceramic materials are extensively used in hermetically sealing alumina electronics packages. Preferred frit glass compositions of this study consist of 37~40wt% PbO, 35~40wt% ZnO, 18~20wt% B2O3, 1~3wt% SiO2, 0~6wt% TiO2. The coated frit glasses crystallize during firing and form a strong hermetic seal. DTA and X-ray diffraction were used to characterize crystallization of the glass frit. Frit seal containing 2wt% TiO2 has crystallization temperature of 550~57$0^{\circ}C$ with surface nucleation. Frit seal containing 6wt% TiO2 has crystallization temperature of 515~5$25^{\circ}C$ with bulk nucleation, and the main crystalline phase was perovskite lead titanate having minus expansion coefficient. The average activation energy for the crystallization calculated from Ozawa equation was 65$\pm$10kcal/mol.

• 한국전기전자재료학회논문지
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• 제11권5호
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• pp.353-357
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• 1998

Cracking problem of Epoxy Molding Compound(EMC) is critical for the reliability of the plastic package during temperature cycling and IR-reflow condition. Fracture toughness of EMC, which is defined as the resistance of EMC to the crack propagation, is a useful factor in ht estimation of EMC against package crack. Thus, development of EMC having high fracture toughness at a given loading condition would be important for confirming the integrity of package. In this study, toughness of several EMC was measured by varying the test conditions such as temperature, loading speeds, and weight percent of filler in order to quantify the variation of toughness of EMC under various applicable conditions. It was found from the experiments that toughness of all EMC has following trends, i.e., it rapidly decreases over the glass transition temperature, remains almost same or little decreases below $0^{\circ}C$. It decreases with the growth of cross head speed in EMC and the weight percent of filler as the degree of brittleness of EMC increases with the amount of filler content.

• 마이크로전자및패키징학회지
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• 제18권2호
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• 전자공학회논문지A
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• 제32A권1호
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• pp.138-145
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• 1995

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

• 전자통신동향분석
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• 제9권1호
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• pp.123-134
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• 1994

GaAs 칩의 저가격, 고성능, 다기능화에 따라 상용 및 군사용 MMIC와 밀리미터파 IC의 이용이 증대되고 있다. 현재 항공 우주, 군용 시장을 지배하는 소량, 고기능의 IC에서 통신 및 차량용의 대량 생산, 저가격으로 이동되고 있다. MMIC의 개발을 위해서는 넓은 영역의 실장 및 interconnection 기술 개발이 선행되어야 한다. 본 고는 MMIC의 실장시 문제점과 해결 방안 등에 관한 내용을 포함하고 있다.

• Journal of information and communication convergence engineering
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• 제12권1호
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• 전자공학회논문지C
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• 제36C권11호
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• pp.55-63
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• 1999

본 논문에서는 패키지의 전기적 특성이 CMOS 디지틀 회로에 미치는 영향을 해석하고 패키지 특성을 고려한 새로운 CMOS It 패키지 설계방법을 보인다. 집적회로 내의 게이트들이 동시에 스위칭 할 때 패키지에 기인한 동시 스위칭 노이즈 (Simultaneous Switching Noise: SSN)가 시스템의 성능에 미치는 영향에 대하여 해석적으로 고찰하여 패키지의 전기적 특성에 의한 제약조건을 만족시키면서 집적회로 패키지를 설계 할 수 있는 새로운 설계 식을 유도하고 이들 식을 이용한 설계방법을 제시한다. 또한 제시된 패키지 설계방 법의 타당성을 검증하기 위하여 0.3㎛ CMOS 회로에 대하여 범용회로 시뮬레이터인 HSPICE 시뮬레이션 결과와 본 논문에서 제시한 해석적 설계 방법에 따른 결과가 일치한다는 것을 보인다.