• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.1
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• pp.39-44
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• 1998

절연체기판으로서는 아루미나 세라믹 기판을 사용하고 전극으로서는 copper를 사용 하여 DBC공정으로 접합하여 제조하였다. 접합재료는 전처리과정을 거친다음 불활성기체 분 위기 하에서 1065~1083$^{\circ}C$의 온도로 1~60분 동안 유지시켜 접합하였다. 본 실험에서 접합 된 세라믹기판과 Cu의 계면의 SEM 관찰 결과 안정된 접합면이 생성되었으며 접합강도는 약 116MPa로 양호한 값을 얻었다. 또한 Al2O3/Copper 접합계면을 ESCA를 통하여 분석한 결과 CuAlO2의 화합물의 생성을 확인하였다. 이 DBC공정은 제조공정의 단순화를 실현시켜 대량생산에 적합함으로 전자부품 모듈생산에 유용하게 적용될 수있을것이다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.71-76
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• 2002

The status of IC industry in Taiwan will be mentioned briefly in the first place. Focus will be mainly on the technology and business of packaging industry in Taiwan. The developments and accomplishments of packaging technology by either research institute or packaging industry will also be introduced. Introduction.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.63-66
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• 2014

In this study, we investigated the effects of Cu TSV on the thermal management of 3D stacked IC. Combination of backside point-heating and IR microscopic measurement of the front-side temperature showed evolution of hot spots in thin Si wafers, implying 3D stacked IC is vulnerable to thermal interference between stacked layers. Cu TSV was found to be an effective heat path, resulting in larger high temperature area in TSV wafer than bare Si wafer, and could be used as an efficient thermal via in the thermal management of 3D stacked IC.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.65-89
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• 2003

Next Highly sophisticated communication generation of the Advanced Electronics and Imaging processing society will require a vast information volume and super high speed signal transport and information instruction. This means that super high technology should be created for satisfying the demand. It's also required the high reliability of the communication system itself, It will be supported the new advanced packaging technology of the 3 Dimensional structured system and system integration technology. Here is introduced the new 3 Dimensional technology for IC nnd LSI packaging and Opt-electronics Packaging of ASET activity in Japan.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.10-17
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• 2024

This paper discusses Chip On Film (COF) technology, one of the key technologies in flexible packaging to enable miniaturization and flexibility of electronic devices. COF attaches Display Driver IC (DDI) directly to a flexible polyimide substrate, enabling lightweight and reduced thickness for high-resolution displays. COF technology is primarily used in high-performance display panels, such as organic light emitting diode (OLED) displays, and plays a key role in portable electronic devices, such as smartphones and wearable devices. This study analyzes the key components of COF and advances in bonding technology. In particular, the introduction of modern bonding techniques, such as thermo-compression bonding and thermo-sonic bonding, has led to significant improvements in bonding reliability and electrical performance. These bonding techniques enhance the mechanical stability of COF packages while maintaining high electrical connectivity in fine-pitch structures. This paper will discuss the future development of COF bonding technology and its challenges and explore its potential as a next-generation display and advanced packaging technology.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.19-24
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• 2016

Along the few nano sizing dimensions of integrated circuit (IC) devices, acceptable interlayer material for design is inevitable. The interlayer which include dielectric, interconnect, barrier etc. needs to achieve not only electrical properties, but also mechanical properties for endure post manufacture process and prolonging life time. For developing intermetallic dielectric (IMD) the mechanical issues with post manufacturing processes were need to be solved. For analyzing specific structural problem and material properties Raman spectroscopy was performed for various researches in Si semiconductor based materials. As improve of the laser and charge-coupled device (CCD) technology the total effectiveness and reliability was enhanced. For thin film as IMD developed material could be analyzed by Raman spectroscopy, and diverse researches of developing method to analyze thin layer were comprehended. Also In-situ analysis of Raman spectroscopy is introduced for material forming research.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.19-25
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• 2008

In this paper, the front end module (FEM) was proposed for 2.4GHz WLAN band by LTCC multilayer application. The FEM was composed of power amplifier IC, switch IC, and LTCC module. LTCC module consists of output matching circuit and lowpass filter as Tx part, bandpass filter as Rx part. Design of output matching circuit for LTCC was used matching parameter from output matching circuit based on lumped circuit on the PCB board. The dielectric constant of LTCC substrate is 9. The substrate was composed of total 26 layers with each 30um thickness. Ag paste was used for the internal pattern as the conductor material. The size of the module is $4.5mm{\times}3.2mm{\times}1.4mm$. The fabricated FEM showed the gain of 21dB, ACPR of less than -31dBc first side lobe and Less than -59dBc second side lobe and the output power of 23Bm at P1dB.

• Proceedings of the Materials Research Society of Korea Conference
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• 1992.05b
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• pp.17-18
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• 1992