• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.531-534
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• 2005

This paper presents a new data line sharing technique for TFT-LCD panels. This technique reduces the number of data driver IC's to half by having two adjacent pixels share the same data line. This in turn doubles the number of gate lines, which are integrated directly on the glass substrate of amorphous silicon for further cost reduction and more compactness. The proposed technique with new pixel array structure was applied to 15.4 inch WXGA TFT-LCD panels and has proven that the number of driver IC's were halved with nearly 41% circuit cost reduction and 5.3% reduction in power consumption without degrading the image quality.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.58-68
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• 1995

Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.2
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• pp.17-27
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• 1977

The special mini-computer was designed with the one-bus line systems employing the integrated circuits, and was studied by the method of easily making the compiler in 16 bits with each instruction fields. When the 160 nano seconds for a fundamental cycle were used, the optimum operating time for a TTL IC was equal to the access time for the main memory unit. As a result, the circuits were very simple, and the simulator functioned well for all the programs.

• Bulletin of the Korean Chemical Society
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• v.24 no.12
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• pp.1805-1808
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• 2003

The simultaneous determination of As(III), As(V), and DMA has been performed by ion chromatography (IC) coupled with inductively coupled plasma-mass spectrometry (ICP-MS). The separation of the three arsenic species was achieved by an anionic separator column (AS 7) with an isocratic elution system. The separated species were directly detected by ICP-MS as an element-selective detection method. The IC-ICP-MS technique was applied for the determination of arsenic species in a NIST SRM 1643d water sample. An As(III) only was detected in the sample. The detection limits of As(III), As(V) and DMA were 0.31, 0.45, and 2.09 ng/mL, respectively. It was also applied for the determination of arsenic species in a human urine obtained by a volunteer, and three arsenic species were identified. The determination of total As in human urines that were obtained from 25 volunteers at the different age was also carried out by ICP-MS.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.10a
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• pp.113-115
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• 2008

This paper shows the method of modeling and simulation of LED driver circuit. Simplified LED modeling is introduced and a driver IC, HV9910, is modeled by implementing the major function blocks. Circuit of buck type converter is constructed for simulation. Simulation includes the internal function of IC and various performances such as LED array current control and dimming. This results show that simulation approach is valid for circuit optimization and reduction of development time.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.2
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• pp.13-22
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• 2008

For the accuracy correction of the micro-positioning industrial robot, micro-manipulator has been devised. The compliant mechanisms using piezoelectric actuators is necessary geometrically and structurally to be developed by the optimization approaches. The overall geometric advantage as the mechanical efficiencies of the mechanism are considered as objective functions, which respectively art the ratio of output displacement to input force, and their constraints are the vertical notion of supporting leg and the structural strength of manipulation. In optimizing the compliant mechanical amplifier, the sequential linear programming and an optimality criteria method are used for the geometrical dimensions of compliant bridges and flexure hinges. This paper presents the integrated design process which not only can maximize the mechanism feasibilities but also can ensure the positioning accuracy and sufficient workspace. Experiment and simulation are presented for validating the design process through the comparisons of the kinematical and structural performances.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.317-320
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• 2016

In embedded system, if firmware code is opened by other company, must devise hardware copy prevention. That guard valuable product. Not used security IC, Suggested platform is source code open method that prevent core code and hardware copy. And that open firmware code for other company programmer. Suggest system security platform based on Corex-M3. that consist of IAP(In-application programing) and APP(Applicataion). IAP contain core code and security confirm code. APP is implement by other company developer using core function prototype.

• Advances in nano research
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• v.15 no.2
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• pp.129-139
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• 2023

Emerge of nanotechnology has affected many aspects of our life and also triggers research studies in many fields. Nano-medicine are proven to be effective in encountering diseases. In the present study, aspects of the applications and effectiveness of nano-medicine in pediatrics patients are studied. In this regard, using experimental data of previous published researches, combination and dose of nano-medicines are optimized using response surface method and neural-fuzzy inference network. The input parameters of the selected multiple nano-medicines are dose and type and the output is the effectiveness of the combinations using IC50 parameter. A detailed parameter study is presented to observe effects of each inputs on the IC50. The results indicate that personalized scaling of nano-medicine is required in therapy of pediatric diseases such as cancers.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.923-928
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• 1986

This paper describes the design and fabrication of a high performance digital tuning analog component integrated circuit that contains a television station detector and decoders(H and L types). When the comparator level sampling method is used, this integrated circuit can be used as a stable channel selector for an external circuit with very large signal variation. It has been fabricated using the SST bipolar standard process and its chip size is 2.2x2.1mm\ulcorner As a result, we have succeeded in fabricating the IC that satisfies the D.C characteristics, and the channel station detector and decoder function.