• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2005년도 춘계학술대회 논문집
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• pp.35-39
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• 2005

This paper presents a method to reduce hysteresis in multilayer ceramic actuator by connecting the actuator with a capacitor in a series circuit. The change in hysteresis with respect to the capacitor was examined. $0.2Pb(Mg_{1/3}Nb_{2/3})O_3-0.8Pb(Zr_{0.475}Ti_{0.525})O_3$ ceramic material was used as a piezoelectric material for the actuator. Displacement of the actuator was measured in a capacitive gap sensor measuring system. In case of inserting a capacitor in a total circuit, hysteresis became dramatically decreased, and then finally the hysteresis value can be reduced below $0.2\%$. It was found in this present study that reducing the hysteresis in the actuator is dependent upon the characteristics of the capacitor in total circuit and also operating frequency.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권1호
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.

• 한국전기전자재료학회논문지
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• 제28권10호
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• pp.658-664
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• 2015

This paper presents an electrical feature analysis of hysteresis curves in memristor differential and intergral control circuit. After making macro model of the memristor device, electric characteristics of the model such as time analysis, frequency dependent DC I-V curves were performed by PSPICE simulation. Also, we made a circuit of memristor-capacitor based on nano-wired memristor device and analyzed the simulated PSPICE results. Finally, we proposed a memristor based differential or integral control circuit, analyzed hysteresis curve characteristic in the control circuit.

• Journal of Power Electronics
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• 제18권5호
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• pp.1585-1594
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• 2018

The estimation of $LiFePO_4$/graphite battery states suffers from the prominent hysteresis phenomenon between the respective open-circuit voltage curves towards charging and discharging. A lot of hysteresis models have been documented to investigate the hysteresis mechanism. This paper reviews and deeply interprets four non-electrochemical hysteresis models and some improvements. These models can be conveniently incorporated into commonly used equivalent circuit models to reproduce battery behaviors. Through simulation and experimental comparisons of voltage predictions and state-of-charge estimations, the pros and cons of these models are presented.

• 전기학회논문지
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• 제68권2호
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• pp.262-268
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• 2019

Previous dynamic models of hysteresis motor use an extended induction machine equivalent circuit or somewhat different equivalent circuit with conventional one, which makes unsatisfiable results. In this paper, the hysteresis dynamic characteristics of the motor rotor are analyzed using the inverse Preisach model and the hysteresis motor equivalent circuit considering eddy current effect. The hysteresis loop for the rotor ring is analyzed under full-load voltage source static state. The calculated hysteresis loop is then approximated to an ellipse for simplicity of dynamic computation. The permeability and delay angle of the elliptic loop apply to the dynamic analysis model. As a result, it is possible to dynamically analyze the hysteresis motor according to the applied voltage and the rotor material. With this method, the motor speed, generated torque, load angle, rotor current as well as synchronous entry time, hunting effect can be calculated.

• 전기전자학회논문지
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• 제16권1호
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• pp.20-27
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• 2012

본 논문에서는 통신, 탐지 및 제어를 위한 원신호의 크기가 시간적으로 변화하고 또한 간섭 잡음의 역할을 하는 교란 신호의 크기도 시간적으로 변화하는 현대전의 상황에서 교란 간섭 신호와 원 신호를 구분하여 원 신호를 디지털신호로 복원하는 확률을 높이기 위하여 본 논문에서는 피드백의 경로에 있는 MOSFET의 실효적인 면적을 디지털 제어 신호로 변경하여 피드백 전류 신호양의 조절하고 히스테리시스의 크기를 조절할 수 있는 IC 회로를 제안하여 설계, 제작 후 측정 및 분석하였다. 병렬 디지털 제어신호에 의한 히스테리시스가 설계 시 예측한 만큼 제어됨을 0.35m-CMOS 공정의 IC 회로를 제작하고 측정하여 증명하였으며 이를 직렬 디지털 제어신호를 제어하기 위한 회로를 설계하여 모의 실험하였다. 또한 교란신호의 크기에 따란 적합한 피드백을 제공하기 위한 제어신호를 모의실험으로 제시하였다.

• 전기전자학회논문지
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• 제15권3호
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• pp.205-210
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• 2011

본 논문에서는 주변의 간섭 잡음의 변화가 큰 RFID 환경에서 입력 신호를 구형파로 복원할 때 히스테리시스의 문턱전압을 디지털적으로 제어하여 신호 수신 신뢰도를 높이기 위한 비교기 회로를 0.35-${\mu}m$ 선폭 CMOS IC 로 제안 하고 분석, 설계 후 모의 실험을 통하여 전기적 특성을 측정, 비교, 분석하였다. 4개의 디지털 비트를 조절하여 제안된 비교기 회로의 문턱전압을 12mV에서 246mV까지 234mV 만큼 제어가 가능함을 모의실험에서 입증하였으며, 그 결과는 회로를 분석적으로 계산한 값과 매우 적은 오차로 일치하였다. 공급전원은 3.3V를 사용하였다. 또한 다양한 입력신호 및 간섭신호의 환경에서 본 논문에서 제시한 가변회로가 잡음에 덜 민감함을 입증하기 위하여 디지털 제어 비트의 조절로 100kHz의 입력신호에 대한 10MHz의 잡음신호의 영향 및 10kHz의 입력신호에 대한 1MHz의 잡음신호의 영향에서 글리치(Glitch) 오류 제거효과가 큼을 예시하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 춘계학술대회 논문집
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• pp.267-270
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• 2002

The accuracy and the dynamic bandwidth are the two most important indices that an inductive position sensor is evaluated with. Eddy currents and magnetic hysteresis affect both of these performance indices. As the modulation frequency of the sensor increases to improve the dynamic bandwidth, the effects of eddy currents and hysteresis also increases, which results in the loss of accuracy. In this paper, a magnetic circuit model of the differential inductive sensor is developed. This model includes the effects of hysteresis and eddy currents. Experimental results confirm the validity of the model. The model predicts that the eddy current effects are not significant below the modulation frequency of 50kHz, as long as the lamination thickness is adequate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.255-258
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• 2003

The hysteresis characteristics of flux-lock reactor, which is an essential component of flux-lock type superconducting fault current limiter (SFCL), was investigated. The hysteresis loss of iron core in flux-lock type SFCL does not happen due to its winding's structure especially in the normal state. From the equivalent circuit for the flux-lock type SFCL and the fault current limiting experiments, the hysteresis curves could be drawn. Through the hysteresis curves together with the fault current level due to the inductance ratio for the 1st and 2nd winding, the increase of the number of turns in the 2nd winding of the flux-lock type SFCL had a role to prevent the iron core from saturation.

• 대한전자공학회논문지SD
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• 제47권11호
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• pp.37-42
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• 2010

본 논문에서는 주변의 간섭 잡음의 변화가 큰 RFID 환경에서 입력 신호를 구형파로 복원할 때 히스테리시스의 문턱전압을 디지털적으로 제어하여 신호 수신 신뢰도를 높이기 위한 비교기 회로를 0.35 마이크론 선폭의 CMOS IC 로 제안 하고 분석, 설계 후 제작하여 전기적 특성을 측정, 비교, 분석하였다. 이론에서 예측한 디지털 제어 비트의 변화에 대한 히스테리시스의 문턱전압의 가변성이 실험에서 잘 일치함을 입증하였다.