• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.285-288
• /
• 2002

In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.

• The Journal of Information Technology
• /
• v.4 no.3
• /
• pp.155-163
• /
• 2001

In this paper, we implemented sigmoid active function which make it difficult to design of the digital neuron networks. Therefore, we designed of the high speed processing of the sigmoid function in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. we designed of MAC operation unit and sigmoid processing unit are proved that it could run of the high speed. On the simulation, the faster than 4.6ns on the each order, we expected that it adapted to the implementation of the high speed digital neural network.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.31 no.3
• /
• pp.473-480
• /
• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• ETRI Journal
• /
• v.37 no.4
• /
• pp.667-676
• /
• 2015

The third-party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256-point Radix-4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high-speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix-4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex-6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2634-2636
• /
• 2002

This paper describers the implementation of cyber apartment internet contents based on HSPLC(high speed power line communication) subscribers networks.

• Proceedings of the KSR Conference
• /
• 2000.05a
• /
• pp.188-194
• /
• 2000

This study is about fault detection and fault area detection of LV circuit in Cab Cubicle system which have control of train to keep safety in High Speed Train. LV circuit is operated with diagnosis system like safety system. In this paper, we suggest a design and an implementation method to detect fault or to detect fault area automatically about LV circuit. The implemented system is tested successfully after implementation of some function. We expect reduction to diagnosis area or repair time by fault area module

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 2003.10a
• /
• pp.219-222
• /
• 2003

Turbo generator system need starter for gas turbine engine. Turbo generator has high rate gearbox for reduce rotating speed. Because a conventional generator could not operate same speed of gas turbine engine. But Recently turbo generator system is directly connected a gas turbine engine with a super high-speed generator. In this paper, starter driver are implemented direct coupled turbo generator system, Which is directly connected 100kW, 60,000rpm gas turbine engine and 25kW 60,000rpm super high speed generator.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.2 no.1
• /
• pp.39-45
• /
• 1997

In this paper, a high speed motor drive system using an indirect adaptive neural network controller is proposed. In the variable high speed motor drives, the speed response can be deteriorated by long settling time and high overshoot. To obtain a good dynamical performance, an adaptive feedforward controller consisted of Neural Network Controller(NNC) and Neural Network Emulator(NNE) is applied. The NNE is used to identify the parameters and characteristics of high speed motor. To train the controller, the weights are dynamically adjusted using the back propagation algorithm. Computer simulation and implementation of the proposed system is described.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.51 no.12
• /
• pp.676-681
• /
• 2002

This paper presents the implementation and experimental investigation of sensorless speed control for a variable-speed PMSM(Permanent Magnet Synchronous Motor) in super-high speed compressor operation. The proposed control scheme consists of two different sensorless algorithms to guarantee the reliable starting operation in low speed region and full torque characteristics using the vector control in high speed region. An automatic switching technique between two control modes is proposed to minimize the speed and torque pulsation during the switching instant of control mode. A testing system of 3.3㎾ PMSM has been built and 90% load test results at 7000r/min are presented to examine the feasibility of proposed sensorless control scheme.

• Journal of Ubiquitous Convergence Technology
• /
• v.2 no.1
• /
• pp.12-17
• /
• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.