VLSI Implementation of High Speed Variable-Length RSA Crytosystem

가변길이 고속 RSA 암호시스템의 VLSI 구현

  • 박진영 (광운대학교 전자재료공학과) ;
  • 서영호 (광운대학교 전자재료공학과) ;
  • 김동욱 (광운대학교 전자재료공학과)
  • Published : 2002.06.01


In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.