• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.73-77
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• 2003

This paper presents a high-speed algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of a two-input maximum circuit to provide a high-speed operation and a low-distortion in the transfer characteristic. The proposed ADC based on the CMOS integrated circuit technique is simple and suitable for implementing a highresolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation-results verifying the circuit performances are agreed with the expected values.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.354-358
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• 1992

This paper describes a development of high speed fuzzy inference circuit for the industrialprocesses. The hardware fuzzy inference circuit is developed utilizing a hardware fuzzy inference circuit is developed utilizing a DSP and a multiplier and accumulator chip. To enhance the inference speed, the pipeline disign is adopted at the bottleneck and the general Max-Min inference method is slightly modified as Max-max method. As a results, the inference speed is evaluated to be 100 KFLIPS. Owing to this high speed feature, satisfactory application can be attained for complex high speed motion control as well as the control of multi-input multi-output nonlinear system. As an application, the developed fuzzy inference circuit is embedded to a PLC (Porgrammable Logic Controller) for industrial process control. For the fuzzy PLC system, to fascilitate the design of the fuzzy control knowledge such as membership functions, rules, etc., a MS-Windows based GUI (Graphical User Interface) software is developed.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.933-936
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• 1993

A high speed fuzzy processor using bipolar technology is proposed in this paper. The hardware system uses a high-speed current-mode membership function circuit and normalization technique. The new membership function circuit generates an ideal membership function of the fuzzy set and its circuit is also simple and available for VLSI implementation. Several techniques have been implemented to speed up response of the processor. The fuzzy processor has been designed and implemented in bipolar circuit technology. The experiments and simulations show that the response speed is below 100ms. It can also be expected that the fuzzy processor can be integrated on one chip and its response time is only about the order of nanoseconds.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.222-225
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• 2003

In this paper the performance of the high speed circuit breaker with fault current detector is described. The operating mechanism of circuit breaker in use is a magnetic actuator and a fault current detector is based on the DSP and A/D converter. The results show that 3-cycle is enough to interrupt the fault current and the more speed up performance is expected with on-going project.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.538-541
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• 1998

This paper describes the development of 5.15ns 32kb asynchronous CMOS SRAM using 0.6.mu.m CMOS technology. The proposed high speed embedded SRAM is realized with optimized control circuit and sense amplifier at a power supply of 3V. Using proposed control circuit, the delay time from address input to wordline 'on' is reduced by 33% and mismatch-insensitive sense amplifier can sense a small difference of bit-line voltage fast and stably.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.2
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• pp.20-24
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• 2010

High speed cutting processes of rigid flexible printed circuit board by making use of high power UV laser with nano-second pulse width have been proposed and investigated experimentally. Also robust laser cutting system has been designed and developed in order to obtain a good cutting quality of rigid and flexible PCB with multi-layers (2-6 layers). Power controller module developed for ourselves is adapted to control the laser output power in the range less than 1%. The systems show the good performance of cutting speed, cutting width and cutting accuracy, respectively. Especially we have confirmed that the short circuit problem due to the carbonized contamination occurred in cross section of multi-layers by thermal effect of high power laser has been improved largely by using multi-pass cutting process with low power and high speed.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.327-331
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• 2008

This paper dealt with high speed breaking method to parallel arcing in low-voltage systems. The proposed high speed breaking circuit consists of a Rogowski coil and an integrator, and operates with an earth leakage circuit breaker (ELCB). A parallel arcing state was simulated by a short circuit using stripped wires. In this test, we analyzed tripping characteristics of the circuit breaker by the length of wires from 5m to 30m. From the experimental results, we confirmed that the proposed method can break the parallel arcing within a few millisecond.